Breakfast Bytes Blogs

Today, at CadenceLIVE Europe, Paul Cunningham, the GM of the verification business unit, announced System VIP. This is another product that broadly falls under the heading of computational logistics. I think of it as logistics for cache-coherent systems. Most complex SoCs contain some form of network-on-chip or NoC. These days, the NoC is almost always cache-coherent, which creates both a whole new class of possible functional errors, and an increase in the difficulty of measuring actual system performance with realistic traffic.

Earlier in his keynote, Paul talked about UPS. They think of themselves as a logistics company. Sure, they have a large fleet of different vehicles such as vans, trucks, and planes. Maybe, one day, drones. These vehicles are obviously all important since they have different characteristics. UPS obviously can't make deliveries to your house with a plane, and although it is possible to drive a van across the country, it takes several days and the van doesn't carry much.

But the most important thing of all is the logistics that make it all work together. This is well summed up in a famous quote by General Omar Bradley, who said: “Amateurs talk strategy. Professionals talk logistics.” To non-professionals, this is almost invisible. For example, at the D-day landings, understood by most people from the opening ten minutes of Spielberg's Saving Private Ryan, the challenges of the actual invasion are very visible. What nobody, even Spielberg, thinks much about is "Where are those guys going to get their dinner? And their gasoline?"

There is a good parallel between UPS logistics to move packages, and using the portfolio of Cadence verification tools to "move vectors". There is simulation with Xcelium, emulation with Palladium Z1, and prototyping with Protium X1. Over the top of that are all the computational logistics products such as vManager.

And, from today, System VIP.

System VIP

I assume everyone knows what VIP is. It is short for Verification IP. This provides a verification ecosystem for a specific piece of IP. The form that this takes will vary depending on the IP. For example, VIP for a PCIe controller will make sure that it correctly executes various aspects of the PCIe protocol. I say "various" because this type of protocol is really complex, and often a given implementation does not need to implement all of it. It is obviously unhelpful to try and verify functionality that was not implemented and clutter up the logs with the evidence that it doesn't work.

System VIP takes the verification level up to the system level. It sits above the existing VIP approaches, which all share the model of providing a stimulus, analyzing the results, and checking for correctness. That bit doesn't change with SystemVIP. So instead of just verifying that, say, the PCIe interface is correct (which you need to do, of course, with regular VIP), it will verify that data arriving on the PCIe interface makes its way through the cache-coherent interconnect and ends up correctly in on-chip memory, and how long it took to get there. Or if the processor reads some data that is held in a non-local cache, the snoops and other mechanics of cache coherency perform correctly and the processor sees the correct data. And how much extra time it took compared to the more common case that the data is already in the processor's local cache.

But that's fairly abstract. What is actually under the hood of System VIP.

As you can see from the logos in the above image, it has been crafted to work on systems based on the three most common processors: x86, Arm, and RISC-V. It consists of four main components:

• System Testbench Generator
• System Traffic Libraries
• System Performance Analyzer
• System Verification Scoreboard

Let's look at each of those components in turn.

The System Testbench Generator provides automated testbench verification:

• Unified input with either IP-XACT or CSV
• The System Testbench Generator creates UVM SV testbench for simulation...
• ...or it generates a C testbench for emulation

The System Traffic Libraries provide libraries for subsystem tests:

• Cache-coherency, performance, PCIe, and more
• These run seamlessly in all of simulation, emulations, prototyping, and actual silicon
• Integrated with VIP and AVIP for fast bring-up

The System Performance Analyzer does just what it says on the can: automated performance analysis:

• Supports memory, interconnects, and peripherals
• Enables performance bottleneck debugging
• Single analysis for both simulation and emulation

The System Verification Scoreboard provides an automated scoreboard on the progress of system verification:

• Checks data and cache-coherency across the system
• Supports interconnect fabrics, DDR, and interfaces
• Supports both simulation and emulation flows

Putting It All Together

Real systems are complicated! The above diagram is not even as complex as it gets. To the top left are two four-core CPUs. To the top right, there's a GPU and display driver. In the middle at the top is a memory management unit. At the bottom are DDR interfaces, a debug unit, and more. These are all represented by the blue boxes. The yellow boxes are VIP and AVIP for individual blocks/subsystems. System VIP consists of the four boxes around the outside of the block diagram. System Testbench Generation at the top works with the System Traffic Libraries to drive the simulation/emulation. On the right, the System Verification Scoreboard checks that everything is performing to spec, largely independent of timing. On the left, the System Performance Analyzer measures everything to do with timing.

The results are a big increase in performance. For example, Arm themselves have been using System VIP in beta. Tram Nguyen, director of design services, found:

By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.

Tomorrow

Paul actually announced a second product a couple of slides later, Clarity 3D Transient Solver. I'll write about that tomorrow.

Learn More

See the System VIP product page. We also have two videos about System VIP.

Introduction to System VIP 

Listen to Nick Heaton, Cadence Distinguished Engineer, as he gives an introduction to System VIP, a new suite of tools and libraries that enables up to 10X efficiency gains in system-level testbench assembly, execution, and analysis for SoCs (12 minutes).

Improve SoC-Level Verification Efficiency by Up to 10X

Chip-level testbench creation, multi-IP and CPU traffic generation, performance bottleneck identification, and data and cache-coherency verification all lack automation. The effort required to complete these tasks is error-prone and time-consuming. Discover how the System VIP tool suite by Cadence works seamlessly with Cadence’s simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes (2 minutes).

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