Breakfast Bytes Blogs

The latest release of the Tempus Timing Signoff Solution, 21.1, contains a lot of new capabilities. There are far too many to cover in a single blog post—the customer presentation on Tempus is 90 slides long. Obviously, that goes into a lot more detail than would be appropriate in a more general interest blog like Breakfast Bytes. Today, I'm going to focus on a group of features that I term "design for robustness".

Of course, timing signoff is of no use if it is not certified with the foundries. Tempus is certified with all the leading foundries down to their most advanced nodes (3nm for those that have it, 7nm or 12nm for foundries that have not adopted EUV).

Customers are using it. I'll just give one example of a North American top 5 semiconductor company and its track record of adoption:

• 2018 The company started using Tempus ECO with 25% of designs
• 2019 A 5nm chip had 75% Tempus ECO usage and deployed Tempus for 40% of new designs
• 2020 Most designs started using Tempus ECO and Signoff
• 2021 Committed more than 90% of design starts at 5nm and below to use Tempus ECO and Signoff

Tempus reduced design closure time by two weeks and was twice as fast running on a single machine. Time to market is a bottleneck for advanced node designs, so, once accuracy is a given, run-time performance, cloud-readiness, and integration with other tools are all increasingly important. Going forward, the challenges can be grouped into three big buckets: increasing design complexity, increasing challenges in modeling, and a customer-centric view of care-abouts like time-to-signoff and the number of iterations required.

Design Robustness

The above diagram shows what is new in the 21.1 release. I'm going to focus on the three small circles on the right, design robustness:

• Timing robustness
• Aging-aware STA
• Tempus Power integrity (PI)

Timing Robustness

Timing Robustness exists alongside conventional signoff slack analysis. It addresses the challenge that simply dropping in 4σ or 5σ limits has a major impact on PPA since it is really over-design. Instead, Timing Robustness is a statistical measure of silicon performance that complements slack. It allows a design to meet its reliability targets (such as 4σ) while improving by several percent the PPA of the design. For instance, one design used Timing Robustness at 3σ compared to classic signoff at 4σ, and reduced power by 8% and area by nearly 12%. These are big numbers. The library has to have LVF (Liberty Variation Format) and, for best results, include moments.

Aging-Awareness

I think I was consulting at Silvaco about 5 years ago when I first came across the fact that transistors change their performance as they age. In older processes, the effect is minimal and it was only the automotive industry with its extended temperature range and 20-year lifetimes that did the analysis. At modern leading-edge nodes, it affects all designs. Although this phenomenon is referred to as "aging", it is not actually driven by the calendar but by the switching of the transistors over the years.

When doing timing signoff, it is not acceptable to just guarantee that the design will function straight out of the fab, it also has to continue to function as all the transistors age through use. Existing solutions are expensive and inaccurate, with excessive pessimism introduced by derating, and fixed age libraries being too inaccurate (not to mention, expensive to characterize). As is usually the case in EDA, the alternative to pessimism is accuracy, which avoids over-design and so improves PPA. The Tempus plus Liberate) flow performs a single stress-independent library characterization and then does a switching activity driven non-uniform aging STA.

Tempus Power Integrity

The Tempus PI flow is built on a seamless Tempus-Voltus integration, with common databases and runtime model (so no file transfers). It identifies voltage-sensitive paths (which are not always the timing critical paths) and aggressors. It performs a sensitivity calculation with machine learning, generating well thought-out activity as opposed to just random activity. Timing and IR drop violations can then automatically be fixed in Innovus.

The benefits are that Tempus can catch timing violations that are missed by today's IR-drop signoff methodology. With this methodology, it is possible to reduce the Max IR-drop margin, get faster timing closure since there is less fixing, and an end result with better PPA (in particular, a higher F_max).

Another Example

I'm not sure what would qualify as the most challenging design around, but a 5G mmWave modem has to be up there. Blu Wireless used Tempus to tapeout its modem, targeted at wireless backhaul and fixed infrastructure. Their care-abouts were:

• 20M-instance design with multiple hierarchies, sub-hierarchies and blocks
• Minimize iterations between implementation and timing signoff
• Concerned about turnaround time for timing ECOs with more than 100 timing views
• Need precise timing ECOs of several multiply-instantiated modules with different orientations
• Minimize leakage power and identify dynamic power savings during RTL development

Result...well, don't take it from me, take it from Blu Wireless's SVP of Engineering, Davide Sarta:

The Cadence Tempus Timing Signoff Solution and Tempus ECO enabled us to achieve our aggressive 5G mmWave design tapeout schedule. The tight integration between the Innovus Implementation System and Tempus Solution delivered reduced closure iterations, significant power improvement, and achieved 1.4X faster design closure time, enabling us to get to market more quickly with the best performing product.

Learn More

See the Tempus Timing Signoff Solution product page.

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