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There was a recent panel discussion at Cadence on the future of EDA. Of course the E in EDA stands for electronics, but that's far too boring in the IoT era, so everyone called it the "cyber-physical" domain. To be fair, that fitted with the academics' view that we need to make EDA sexier. Cyber-physical certainly sounds sexier, like we are all going to be Terminators or something.
Joking aside, it was a serious discussion. The session was moderated by Alberto. Like Madonna, at least in this industry, he only needs one name, especially as his last name is so long that he sometimes must have problems filling in computer forms. It's Sangiovanni-Vincentelli, and he is one of the the pioneers in EDA at UC Berkeley (the others being Ernest Kuh, who died last year, and Richard Newton, who unfortunately died young almost exactly 10 years ago). He was one of the founders of SDA and thus Cadence, which was created when SDA merged with ECAD. He also was one of the founders of Synopsys. He has been on the board of Cadence for almost 25 years.
He also received, among very many awards, the Wolfson James Clerk Maxwell award from the Royal Society of Edinburgh, which gives me an excuse to tell you that I spent the entire time doing my PhD in the James Clerk Maxwell building. You might assume from that fact that he worked at Edinburgh University for years, but in fact he was turned down for a lectureship and so went to Cambridge. He was only ever a student at Edinburgh. The JCMB, as it is known, is just across from the Darwin building. Yup, failed his second year medicine and left...for Cambridge. Now you know the recipe for getting a building named after you in Edinburgh. Be unsuccessful and then go to Cambridge. Oh, and then change the world. Wofson, in case you were wondering, made his fortune as the owner of a mail order catalog company, roughly the equivalent of the Sears catalog in the US, although I don't think that they had physical stores until much later. Perhaps I should call him the Jeff Bezos of his day.The panelists consisted of two members of the Cadence executive staff, and two Cadence-sponsored professors. The professors were Kameshwar Poola of Berkeley and Kunle Olukotun of Stanford. The executives were Anirudh Devgan, who runs both the digital and signoff group and the systems and verification group, and Chi-Ping Hsu, who is the chief strategy officer.
Since immigration is in the news with the recent election, it is worth pointing out that everyone on the panel came from somewhere else. Alberto (Italy), Kameshwar (India), Kunle (Nigeria), Anirudh (India), Chi-Ping (Taiwan). Even me (UK). And Richard Newton and Ernest Kuh, who I mentioned above (Australia and China).
Alberto went first. He emphasized that he was taking a broader view, not looking just at EDA as it is defined today, but at all of electronics, The Landscape of Opportunities. He brought up the term cyber-physical domain. Later, during the questions, it turned out that there is a course at Berkeley called CE186 Designing Cyber-Physical Systems, although the basis is still tools. What are cyber-physical systems? Think things like industrial internet (intelligent machines, advanced analytics),or smart cities (smart water, smart traffic, smart energy).
Predictions are for the immersed human, with about 1000 devices per person by 2025: 7 trillion devices and 7 billion people. One big opportunity for EDA is making this all work together, "move plug and pray, to plug and play." Not that this is directly EDA as we think of it today, but it has a lot of the same algorithmic and complexity issues.
Kameshwar Poola was next with Data Analytics in NextGen EDA. The landscape for design is challenging with new technology, exotic materials, a breakdown of the design/manufacturing interface, and some complex ownership issues about data. These are areas where data analytics can help:
But, he cautioned, deep learning and big data are very useful but it is dangerous to ignore fundamental physics. He used OPC/RET as an example, where the area affected by any polygon is now getting so large that it is computationally prohibitive. This shows up in the well-known problem of design rule counts exploding with each process generation.
He moved on to cyber-physical systems with some examples: unmanned autonomous systems, robotics for assisted living, and so on. The key features are uncertain environments and complex system dynamics. There are three central problems:
Again, this is not traditional EDA but there is a mathematical resemblance to core EDA problems. As a result, he pointed out, Cadence talent already has many of the skills needed.
One place that this talent might not be coming from are the universities. Electrical engineering applicant numbers are dropping at all major universities as more and more students select computer science. And they are not studying EDA in those computer science courses, they are learning how to write apps. He said that EE143 (microfabrication technologies) has dropped 50% since just 2012, EE144 (algorithms for system modeling) has dropped 60%. He thinks that the problem is that it takes work to learn this stuff and many young people feel it is easier just to write an app.
Kunle Olukotun came next, to give the Palo Alto view from across the bay with Scaling Application Performance with Moore's Law. He pointed out that the title should really be Scaling Data Analytics with Moore's Law, the developing theme of the morning. This is truly the golden era of data, incredible advances arrive by the day with no end in sight. All the action is in engines, whether co-processors or programmable (FPGA).
He echoed Kameshwar's point that there is a big gap between "the type of programmers who develop apps” and those who understand OpenMP, Cuda, Map Reduce, and Verilog/FPGA. He called this the programmability chasm. His research area is high-performance domain specific languages (DSLs). The basic idea is to develop a framework for DSLs (his work goes under the name Delite) and can then scale up with big data analytics and Moore's Law.
He showed the programmability versus efficiency tradeoff, based on analysis of chips from ISSCC. There is a 1000X difference in efficiency from dedicated designs to programmable CPUs. He reckons that systems like Delite can get the cost of software down, but we also need to get the underlying cost of SoCs down with software-defined hardware (SDH), with reconfigurable datapath elements architected for data analytics with a DSL compiler. The advantage of SDH is closing that 1000X gap, with 100X performance/watt compared to a CPU (10X versus a GPU), and 1000X more programmable than an FPGA solution (not sure how you measure that).
We talk about PPA in modern SoC design. Kunle thinks we can have all of PPPP: power, performance, programmability, and portability.
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