Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week before in the Santa Clara Convention Center, but got pushed out a week and moved to the San Jose Convention Center. IEDM is in San Francisco, so I mostly attended IEDM but I came down to San Jose for much of the first day of the RISC-V Summit. I'll cover that today.

I have been following the RISC-V story since EDPS 2016 in Monterey when I first heard about it. If you don't know what RISC-V is (and you might therefore not know it is pronounced "risk five") then see my posts:

• RISC-V—Instruction Sets Want to Be Free
• RISC-V Summit Preview: Pascal or Linux?

In January this year, in a post titled RISC-V Cores: SweRV and ET-Maxion, I wrote:

The one-sentence summary of the state of RISC-V is that it is already dominant in academia, and has some traction with the defense industry, too. I doubt any chips will be built in academia that are not RISC-V-based, and it is clear that a lot of ideas for things like hardware security will be prototyped in RISC-V. The big question is how significant it will be in the commercial world.

That's a pretty good summary of what I saw in this year's summit. There is lots of progress in the standardization process, building out the software ecosystem, growing the RISC-V foundation, and more. When Rick O'Connor was running the RISC-V foundation (he's now running the OpenHW Group) he told me that there was a huge funnel of products from big names that hadn't yet been announced. But not a lot that met that description was announced this year, apart from Samsung (see below). At last year's conference, Rick also said:

There will be more than 10 million but less than 100 million chips containing RISC-V processors shipped in 2019

Major Companies

Here's who has announced projects for production (as opposed to research projects):

• NVIDIA announced three or four years ago that the control processor in their GPUs would switch from an internal design with a proprietary instruction set, to an internal design with the RISC-V instruction set. GPUs have a design cycle that I would guess is a couple of years, so I don't know if they are shipping any GPUs containing RISC-V, but that would certainly count as high volume.
• Western Digital announced last year that they would use RISC-V as the processor in all their products...eventually. They ship 1B cores, expected to grow to 2B. They also announced last year that they had designed a core, SweRV and that they were open-sourcing it. This year, Martin Fink, their CTO, was back giving a keynote and he announced that they will "soon" be taping out their first SoC containing the processor. He said that chip would ship in volumes of "a few hundred million" once it goes into full production. At the summit, they also announced two new cores, the SWerV EL2 and EH2, that they will also open-source.
• Qualcomm announced last year that they would ship a "volume product containing RISC-V in 2019". I don't know if they did. Since they have focused back onto 5G, it's possible that the product didn't make it to production. Their investment arm invested in a few RISC-V companies, but investment arms of semiconductor companies mainly make investments to leverage their cash, and you can't always read anything into those tea leaves.

• Junho Hu of Samsung revealed this year that it taped out its first RISC-V core in 2017. They will be using RISC-V cores in automotive, AI, and 5G mmWave. They also said that "they would adopt in flagship mobile devices in 2020." I will be very surprised if they produce a true RISC-V-based application processor, more likely they will use it for some of the modem and other offload processing. After all, if their mmWave modem for basestations uses RISC-V, it would be natural to use it in the handsets, too.
• And...that's it for major companies announcing actual products.

But maybe this is like Arm in servers. Arm have been trying to get into servers for years, and it didn't really seem to be going anywhere. Their partners got in...and got out again. I think the only partner who has server chips available is Cavium, now part of Marvell. Then, just a few weeks ago, Amazon/AWS announced Graviton 2 (see my post  Xcelium Is 50% Faster on AWS's New Arm Server Chip), which they are sufficiently committed to that they will use it to run much of the management software than undergirds their AWS business. But that is nearly a decade since Arm first took aim at the server market. RISC-V may be similar. After all, Western Digital, the company most committed (at least publicly) to RISC-V still hasn't taped out their first chip.

Calista Redmond, the CEO of the RISC-V Foundation (last time I met her, she was running the OpenPower Foundation), said in her opening welcome presentation that there are:

millions of cores shipping from NVIDIA, Western Digital, SiFive, and others

Since Western Digital has not taped out its first chip, and SiFive is mainly in the IP licensing and design services business, I'm not sure how much to read into that. The fact that she didn't mention Qualcomm may or may not be significant.

State of the Union

But there is undeniably a lot of interest. Calista said that the RISC-V foundation has grown to 440 members (including Cadence) in 41 countries, an increase of 50%. One datapoint: when there was a RISC-V event in Pakistan, not the first country anyone would pick as a major player in semiconductors, there were over 3000 people attending.

Krste Asanovic, the UC Berkeley professor who led the team that originally created the RISC-V ISA, summed up his state-of-the-union keynote with:

• Core standards ratified
• Widespread acceptance and adoption
• Community growing and growing
• Software ecosystem filling out nicely
• Standards efforts filling in gaps
• Lots of work ahead

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