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At the recent CadenceLIVE Americas, Cadence's Yuval Shay presented Think Outside the Chip: A Comprehensive RF Flow for IC, Package, and Module Design. Before cellphones and Wi-Fi, radios were not that common, and RF design was even more of a black art than it is today. Today, radios are ubiquitous. Indeed, you probably have several in your pocket. Your smartphone supports multiple bands, Wi-Fi, and Bluetooth. If you have a 5G phone, then that involves at least two radios, one for the sub-6GHz spectrum, and one for the mmWave spectrum. Of course, there are basestations, too, with more radios. And you almost certainly have a Wi-Fi router at home. In short, radios are everywhere, and that means RF is everywhere.
In general, radios are not built on the CMOS SoC that forms the heart of whatever device is having a radio interface added. At the very least, the power amplifier is going to be off-chip. Radios are most often built in non-CMOS technologies, although passive devices such as inductors and capacitors can often be built most economically on-chip. But building a whole radio is typically done at the module or board level. Today, "module" might mean system-in-package, since there has been so much development in advanced packaging in the last few years. The implication of that is that there are a lot of sub-parts to a radio that have to work correctly together.
A major cause of re-spins of RF designs is module-level connectivity failure, hooking up the signals wrong. Until recently, there were no tools that allowed you to implement the whole flow in an integrated manner. Instead, disjointed tools across multiple teams, each storing a fragment of the design, has been the norm. So different design teams (IC, module, package) all have to communicate but it is all too easy to miscommunicate given different scaling factors, chip orientation, different pad and pin names, and so on. It's all too easy to ask for a pad to be moved a distance to the "left", without that being clear.
Furthermore, every dBm counts. RF engineers really care about system performance. As a result, they spend much of their time in system analysis and performance tuning, using multiple parasitic extraction methods and multiple electromagnetic (EM) solvers, in a constant quest to increase analysis fidelity and accuracy. That is followed by how much trust they have in manufacturing, and building up confidence that the manufacturing process will match up to what they designed. Indeed, it can be a challenge just to ensure that the design analyzed and the design sent to manufacturing are one and the same. Never mind keeping up with all the S-parameters to make sure that the design analyzed was the same as the one looked at in the system context.
These are not theoretical problems. The above diagram shows some of the things that we have seen in the past. On the left are fatal errors that required a re-spin. On the right are challenges that are mainly inefficiency and waste that result in making less money than planned due to increased design and/or manufacturing cost.
Cadence's solution to these problems is the Virtuoso RF Solution. Three big high-level features of the Virtuoso RF Solution are:
There is always a single golden schematic view to drive layout simulation, circuit simulation with EMAG models and RC parasitics, physical verification, signoff, and more. This leads to a golden layout view that is integrated with the EM simulators, automatic layout simplification, and instance-based and net-based model generation. For signoff, there is automatic creation of Smart View with integrated S-parameter models, which can be combined with Quantus RC extraction, and then multiple scenarios can be simulated with Virtuoso ADE Assembler.
Edit-in-concert allows you to simultaneously open layouts across multiple technologies and fabrics, and then edit one fabric in the presence of other fabrics, with a lot of constraints automatically maintained. For example, moving I/Os of the die footprint in the package layout moves I/Os in the IC layout, so it is easy to align ICs with module bumps. You can probe a net across fabrics since the Virtuoso RF Solution understands the golden schematic and how all the different fabrics fit together to implement it.
The Virtuoso RF Solution is integrated with Quantus Extraction and with four EM solvers: Sigrity, EMX (for planar on-chip passives in foundry processes), AWR AXIEM (for more general, not necessarily CMOS, solutions), and the fully-general Clarity 3D Solver.
That this is all an integrated analysis environment means that the user does not have to worry about:
But it's not just at the chip-package level, the same technology extends across all fabrics from chip, to package (including modules and SiP), to board.
Virtuoso RF Solution provides for:
For more details, see the product page Virtuoso RF Solution.
Also, there is an on-demand webinar series (three webinars) also titled Think Outside the Chip.
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