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In October, we held the CadenceCONNECT: Mission Critical event, focused on aerospace and defense (A&D). Tom Beckley gave the opening keynote. By background, many of the senior people in A&D historically knew little about electronics, never mind semiconductors. As the electronic content of everything in these industries has gone up, they have needed to learn, but Tom took as his starting point that his audience knew little about Cadence. As a result, his keynote was a great introduction to Cadence and an overview of our portfolio of tools, hardware, and IP. His keynote was titled Addressing Complexity: Intelligent System Design.
Tom runs R&D for the Custom IC, Packaging, PCB, and Multiphysics Systems businesses, with more than 1300 electrical engineers, computer scientists, technologists, and, increasingly, mechanical engineers. He has spent nearly 40 years in the business, chasing Moore's Law and working on complex electro-mechanical designs. It is incredible to realize that it is only 60 years ago that Jack Kilby and Robert Noyce invented the integrated circuit. This led to the creation of many great semiconductor companies.
Tom started his career in 1981 designing rad-hard semiconductors for military and space applications at Harris Semiconductor (which became Intersil and is now part of Renasas) at Palm Bay, Florida. Moore's Law has driven technology and even transformed society. But the current industry trends—5G, autonomouos vehicles, datacenters, and so on—require immense processing power, integrated hardware and software, and seamless communications. In effect, practically every industry has been "electronified".
Moore's Law, that the number of transistors on a chip doubles every 18-24 months, has driven the industry for decades, but the CMOS scaling limit is approaching at around 1nm. And while these advance FinFET and Gate-All-Around nodes may be appropriate for high-value, high-volume applications, this is not true for low-volume applications.
In the future, companies will add value with advanced packaging, also known as More than Moore as we mix and match different technologies: digital, analog, RF, high-voltage, sensors, photonics, and more. As a harbinger of this, The International Roadmap for Semiconductors changed its name to The Heterogeneous Integration Roadmap. Another implication of this sea-change is that analysis will become much more challenging since everything is 3D: signal and power integrity, thermal, electromagnetics, structural, and more.
Right now, despite the pandemic, Moore's Law (advanced process) and More than Moore (3D systems) are simultaneously booming. Hyperscalars like Google, Facebook, Amazon, Microsoft, and others are simultaneously integrating heterogeneous systems, including their own domain-specific processors. Net-net, while Moore's Law advances towards its atomic scaling limit, the More than Moore trend of integrating sensors, communication, memory, advanced processors, and complex software are pressuring every industry to reinvent itself.
Historically, Cadence has been a leader in electronic design automation (EDA) including digital, analog, and mixed-signal semiconductors. And IC packaging, and PCB design. We've extended our capabilities into FinFET, 3DIC stacking, RF and mmWave, photonics, hardware/software co-design, and analysis. As we exploit our expertise in computational software, we are adopting and using the power of massive parallelism, distributed processing, and machine learning. Cadence's Intelligent System Design strategy is all about dealing with complexity and is why Cadence invests 40¢ of every sales dollar in R&D.
Our next-generation full flow includes Genus and Innovus iSpatial unified physical optimization technology. Machine learning has been layered in to enhance PPA, predictability, and turnaround time.
We have a broad IP portfolio including out silicon-proven Tensiilca processors, analog PHY interfaces, standard-based IP blocks, verification IP, and other solutions, as well as customization services.
We have a broad system and functional verification portfolio. This includes JasperGold formal verification andXcelium logic simulation for digital simulation. The Palladium Z1 emulator extends and reuses your existing simulation environment and accelerates it far beyond the speed of software simulation, and using the Protium S1 FPGA prototyping system, teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development and system regressions.
Cadence has led the industry in providing options for design groups that want to make use of the cloud. Our offerings are divided into two major categories:
All the models have access to cloud-ready Cadence tools.
Next, Tom moved on to his own domains: custom design, PCB, packaging, and multi-physics analysis. If you've done any analog design over the last 30 years, you likely used the Virtuoso environment. For the last 10 years, we've been adapting VIrtuoso for other aspects of design such as sensors, RF, advanced IC packaging, and photonics. You can literally co-design the chip and the package at the same time, optimizing performance and minimizing area. This required a complete rearchitecting of the Virtuoso platform, including a new underlying database.
Cadence's Spectre simulation platform is the industry's leading solution for accurate analog, RF, and mixed-signal simulation. The foundation of the Spectre platform is a unified set of technologies shared by all the engines. This guarantees consistent evaluation methods regardless of the simulator selected. Last year, we introduced the next-generation Spectre X simulator, which addresses large-scale verification challenges with up to 10X speed and 5X capacity improvements, and massively scalable for cloud computing.
5G is massively complex, much more than LTE (4G). Silicon photonics and wafer-level packaging are required. Radio beamforming is a requirement. All of this will require a variety of approaches, which is why Cadence acquired AWR and Integrand earlier this year. Our capabilities now extend from chips (Si, GaAs, etc) to RF modules and RF PCBs.
We have enhanced our design solutions to fully support the layout and analysis of chiplet-based architectures and heterogeneous integration. All of the Virtuoso, Allegro, and Innovus environments have been enhanced to be 3D-aware.
More than Moore includes modules and miniature PCBs, such as the Bluetooth hearing aid in the image contains a miniaturized rigid-flex design, antennas, battery terminals, microphones, speakers, and more. But whenever we miniaturize and put boards and devices into small enclosures, we need to worry about thermal, and how IR increases at higher temperatures, stressing the electronics.
Cadence is investing significantly in AI and machine learning. Tom said that in his team of over 1300 people in R&D, he has over 50 PhDs working on machine learning for chip, package, and PCB design. Across all of the company, we have hundreds working on AI and ML. For example, our JasperGold formal verification solution uses machine learning to enhance proof completion and to increase overall throughput.
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