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Today at the TSMC Technology Symposium, Cliff Hou, TSMC's VP of R&D, is set to announce the latest member of TSMC's process portfolio, 12FFC. Of course, given the name, you will guess that this is a process derived from 16FFC, the third generation process that TSMC introduced for consumer products (although the "C" actually stands for "compact"). The 16FFC process has been in volume manufacturing for a year or two, and your smartphone almost certainly contains some silicon from it.
I haven't seen the widths and spacings of the new 12FFC process, and I'm writing this post ahead of seeing exactly what information Cliff discloses (more on that in a couple of posts I plan for next week). In particular, I don't know whether12FFC is a true shrink from 16FFC so that moving a design from 16 to 12 should be... well, I was going to say "straightforward", but nothing down at these geometries is straightforward, due to requiring more double-patterning, new EM restrictions, worse self-heating, and so on. And, as you can expect, Cadence is announcing support for this process this morning.
Cadence is also announcing certification on version 1.0 of TSMC's 7nm process, that they simply call 7nm (I don't think trademark law allows them to stop anyone else calling their process 7nm though, but don't take legal advice from a writer).
A third announcement that went out on Monday, is a more complete support for TSMC's InFO packaging solution.
Of course, all these processes are in support of TSMC's high-level strategy to focus on four fast-growing market segments:
The 12FFC process is targeted at mid-range mobile and high-end consumer applications that require optimal PPA. Cadence is actively engaged with early customers. Both the digital and signoff, and the custom/analog tools have achieved certification against this pre-release information. Cadence has also delivered a library characterization flow and is developing IP for customers migrating to this process. A new PDK is available for download.
The entire Cadence flow is supported; in particular:
TSMC see this process as the stepping-stone between 16FFC and 7nm for area and power sensitive designs (well, all designs are area- and power-sensitive, but the HPC segment, in particular, wants performance above all else, and will pay in area and power to get it; the other markets, not so much).
Cadence digital, signoff and custom/analog tools have achieved certification for V1.0 design rules and SPICE rules for the TSMC 7nm process. We have delivered a new PDK enabling optimal PPA, and additionally, the 7nm reference flow and the library characterization flow have been enhanced. The 7nm DDR4 PHY IP has taped out and is already in deployment with customers who have incorporated it into enterprise-grade SoCs.
New features in the digital flow include via-pillar modeling in Genus synthesis and full via-pillar capabilities in the implementation and signoff environments. Additionally, clock mesh handling and bus routing capabilities support the high-performance library to deliver improved PPA and mitigated EM impact.
The custom/analog tools have been enhanced to include advanced device snapping and an accelerated custom placement and routing flow that enable the customer to improve productivity while meeting power, multiple patterning, density and EM requirements.
The layout implementation module in the analog/custom environment includes connectivity and constraint-driven layout, as well as a row-based methodology for FinFET device placement that lets designers avoid DRC violations and address layout-dependent effects. The routing module offers a color-aware flow and track pattern system that reduces design time, minimizes parasitics and helps designers avoid EM issues.
Th Liberate and Variety characterization solutions have been validated to deliver accurate Liberty libraries for the process including advanced timing, noise and power models, and variation encapsulated in LVF.
Cadence has announced an integrated flow that provides system-level planning capabilities and accurate modeling of cross-die interactions for mobile and IoT applications (InFO is targeted and low and mid-range systems (TSMC's other 3D packaging technology, CoWoS, is targeted at high-performance designs for high-end FPGAs and HPC).
Using the Cadence suite of tools, designers can:
To learn more about the Cadence solutions on 12FFC, please visit our website: