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Paul McLellan
Paul McLellan

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TSMC
TSMC Technology Symposium

TSMC: Zero Excursion, Zero Defect

3 May 2019 • 3 minute read

 breakfast bytes logoAt the recent TSMC Technology Symposium, JK Wang, the SVP of fab operations, talked about Manufacturing Excellence. There were two parts to this:

  • Capacity ramping and new fab status
  • The pursuit of quality excellence

Capacity Ramping and New Fab Status

There were lots of aerial photos of fabs under construction, but unfortunately, they don't let us either take pictures of the screen nor give us copies. You'll just have to imagine them. TSMC plans very limited ramp from 2018 to 2019 of 2%. Total capacity will be over 12M 12" wafers.

JK showed pictures of the ramps for various processes. N40 and N28 were gradual and took place over 36 months, but N16 ramped in three months, and N7 even faster. N10 and N7 capacity doubled last year from 2017, and will be up 3X in 2018 (from 2017). The monthly capacity is around 100,000 and annual capacity of over a million wafers.

Fab 18 is a brand new fab adjacent to Fab 14. Don't forget that when TSMC says "fab" they mean a huge operation, and when they say "phase" they pretty much mean fab. There are three phases at various stages of construction in Fab 18. Tool installation was started in the P1 clean room in February this year. N5 production is to start in 2Q 2020.

Here's a picture of fab 14A next door from TSMC's press gallery, to give you some sense of scale.

The Pursuit of Quality Excellence

The phrase JK used is the one I used for the title of this post: Zero Excursion, Zero Defect.

You know what a defect is, and obviously, zero defect is a goal that is not completely achievable. An excursion is when you lose the process completely so that nothing is yielding, which can be for many many reasons. Here's why zero excursions are so important:

There were rumors of an excursion late last year. In February, TSMC put out the above press release. In this case, it was bad photoresist in Fab 14B. It cost them $550M. Some of that will be recovered in Q2 when they remanufacture the scrapped wafers.

As JK stated during his presentation:

We recently had a manufacturing incident. Our manufacturing force has emerged better and stronger.

Three programs they have strengthened:

  • Early detection and stop and fix
  • Automotive maverick lot
  • DPPM reduction

The things he mentioned about early detection and stop and fix was to leverage AI methodologies to detect line abnormalities such as upward/downward shift, cyclic effect, long-term baseline shift, variance shift, mismatch of tools (different equipment giving different results).

They now have a smart sampling system, including KLA measurement wafers. (KLA Tencor is an equipment maker who focuses on measurement, I assume that is what this is referring to.)

They do wafer uniformity monitoring, inspecting 4-500 times the number of points they used to. They can detect in-wafer variation. If variations are found, the tool is stopped and fixed.

They are using convolutional neural networks (a type of vision processing) to do feature extraction and classification of defects, with an aim to reduce defect escape rate and to perform proactive predictive maintenance.

For automotive, they have a new tighter spec leading to baseline process improvement. They now screen out good die in a bad zone: if a die fails test, then not only that die but its neighbors are "inked" and marked as bad. There is 100% outgoing inspection for automotive (normally just nine sites for regular non-automotive).

The maverick lot refers to when wafers in a lot are scrapped. In that case, the other wafers in the lot are scrutinized and the customer is told they come from a maverick lot.

They are doing a lot of work on edge engineering across many modules and process nodes. Due to all sorts of reasons, die in zone 4 (the outermost quarter of a wafer) have more issues than zone 1 (the center). The improvements that they've seen from 2014 to 2108 are largely from wafer edge.

They also collaborate with customers on screen rules (since TSMC is a foundry, it doesn't really know what's on the die in detail), which gets 25% further improvement.

N16 took three years to get below 10 DPPM. JK anticipates N7 will be faster still.

 

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