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A quick guide to TSMC processes. There is a 10nm process but very little development is being done at that node. It is like the mad wife kept in the attic like in Jane Eyre. It seems to be primarily for production of the big names in mobile. In general, anyone in the high-performance area not on a very short lead-time is going straight to 7nm (for example, Xilinx is skipping 10nm). There is a new version of the 7nm process called 7nm+. Also, there is an optical shrink of 16FFC called 12FFC. These are the processes where the most active development is going on. Of course there are older processes, and presumably one day there will be whatever comes after 7nm.
Cadence flows obviously are supporting these processes. Various updates were announced a few days before TSMC OIP Symposium. I am only going to talk about new stuff for these processes and I will take as given the base digital, signoff, and custom/analog flows. This post assumes you are familiar with the Cadence product offerings, and if you are not there is plenty of material on the Cadence website.
7nm+ is a high-performance process targeted at HPC and high-end mobile applications. The digital, signoff, and custom/analog tools have achieved certification on this process. In addition, enhancements were made to the library characterization flow.
In parallel, with several testchip tapeouts completed, we have broadened our support for 7nm technology.
Digital tool capabilities specifically designed for the 7nm+ process include EUV layer support, elimination of double-patterning requirements for some metal layers, cell pin support, and expanded via-pillar and autoNDR support. Digital and signoff flow enhancements for the 7nm process include congestion and IR-driven placement, improved clock buffer clustering/placement/routing, and engine improvement in the NanoRoute tool for runtime and design rule check (DRC) quality.
In the analog world, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies when designing using the 7nm+ and 7nm process technologies. Early customers have been able to maintain similar cycle times to the 16nm process by using the tool’s advanced-node capabilities like multi-patterning and color-aware layout, module generator (ModGen) device arrays, automated FinFET placement, and variation analysis.
In addition to the tools certified for TSMC's 7nm+ and 7nm process technologies, the Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise, and power models for the 7nm+ process. The solutions use innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for ultra-low-voltage applications and creating EM models that enable signal EM optimizations and signoff. Bottom line: You can use these tools to characterize 7nm and 7nm+ libraries and get the data required for the flows to work correctly.
Also, we announced that the digital, signoff, and custom/analog tools and flows have achieved v1.0 certification for current process design kits (PDKs) for TSMC’s 12FFC process technology and are production ready for customers wanting to deploy 12FFC. In addition, Cadence IP is ready for design starts on the new 12FFC process.
The Cadence digital and signoff tools offer a number of floorplanning, placement, routing, and extraction enhancements required for the 12FFC process technology, including improved pin access, M2/M3 rule compliance, electromigration (EM) fixing, via0 alignment/via1 insertion, PG cell handling, and colorless TechLEF support. New enhancements since March 2017 include inbound and outbound cell simultaneous placement for optimal timing closure and comprehensive support for routing halos. For custom/analog, the Cadence Virtuoso Advanced-Node Platform provides underlying support and capabilities for the TSMC 12FFC process, enabling better designer productivity over traditional manual approaches. Some of these features and capabilities include snapping grids for placement of devices, module generator (ModGen) array generation, advanced track patterns for routing, a state-of-the-art wire editor, automatic routing features, and in-design design rule checks (DRCs) and constraint checking for correct-by-construction layout.
Cadence digital, signoff, and custom/analog tools receiving v1.0 certification for 12FFC include the Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS), LDE Electrical Analyzer, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF option, and Spectre Circuit Simulator, as well as the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment, and Virtuoso Integrated Physical Verification System.
In addition, the Cadence Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver accurate Liberty libraries for the TSMC 12FFC process including advanced timing, noise, and power models.
Basically, this is complete support for the digital, signoff, and custom/analog flows, along with full library characterization capabilities.
In addition to these tools that have been optimized for the 12FFC process technology, a full suite of interface IP is under development to support this process. Cadence recently taped out its 4266 speed-grade LPDDR4/4X PHY, which will be complemented by key Cadence mobility IP suites including MIPI D-PHY, PCIe 3.0 PHY, USB 3.1/2.0 PHY and DPv1.4 PHY IP. The mobility suites are targeted at application processors as well as high-end consumer and IoT applications.
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