Breakfast Bytes Blogs

Cadence, TSMC, and Microsoft are presenting a joint webinar on December 2 (in a couple of days' time). The title is Beat Your Signoff Schedule! How to Sign Off a 10 Billion+ Transistor Design in the Cloud, and the presenters are:

• Vivian Jang, Technical Manager, TSMC
• Kurt Chiang, Technical Manager, TSMC
• Prashant Varshney, Sr Director Product Management Azure Engineering-Silicon Microsoft
• Brandon Bautz, Sr Group Director Product Management, Cadence
• Ketan Joshi, Group Director Cloud Business Development, Cadence

The most important part of the abstract is:

In this CadenceTECHTALK, TSMC + Microsoft + Cadence will present a signoff methodology optimized for giga-scale class (10 billion+ transistor) designs and tailored for execution on cloud-based infrastructure. The talk will feature the Cadence Tempus Timing Signoff Solution’s STA signoff tool and CloudBurst platform, as well as Microsoft Azure’s latest offerings suited for EDA workloads.

One of the big appeals about running EDA tools in the cloud is the way that the compute resources can scale. Different phases of design have different requirements, both in terms of the number of servers and in the resources (such as memory) required in the servers. The most scalable task of all is probably library characterization, since every cell and every corner are independent. There is really no reason that you can't use literally tens of thousands of servers, and we have done experiments using over 50,000 cores.

The next most scalable task seems to be signoff, and many design groups with on-premises (on-prem) data centers will "burst to the cloud" for signoff since the peak internal resources are insufficient. Of course, signoff comes at the end of the design cycle (along with physical verification) and so the time to complete signoff seems especially critical, almost the last thing before tapeout. The Tempus technology has been optimized for cloud in the sense that it runs in distributed fashion on "normal"-sized servers, without the need for servers with enormous amounts of memory. 

I have written about signoff in the cloud a couple of times before:

• In 2019, Barefoot in a CloudBurst: Tempus on 2000+ CPUs (some of the earliest work on Cadence Cloud)
• Last year, TSMC, Microsoft, Cadence: Signoff in the Cloud (last year's cooperation between the three companies has continued in 2021)

A lot has changed in the last few years. As always, designs have got bigger with some designs measured in the tens of billions of transistors. Cloud infrastructure has matured, too. Although some design groups operate entirely in the cloud, the focus of this webinar is doing timing signoff with Tempus and the Cloudburst platform. Tempus is optimized for Cloud distribution. Tempus distributed STA (DSTA) has the same accuracy, and a lot of smaller instances are a lot cheaper than a huge server. Using smaller instances also makes it easier to use reserved instances rather than the more expensive pay-as-you-go instances. For some other tasks, such as library characterization and simulation regression, which consists of large number of small jobs, even cheaper spot instances, which can be pre-empted and restarted, can be an even better solution, but they are not so appropriate for Tempus DSTA.

The graph above goes up to 14B transistors based on data from Semianalysis, but I'm sure you've heard announcements during 2021 of much larger chips, too. Tens of billions is the new normal, and I'm sure will go bigger still as 3nm comes into production.

What the Webinar Will Cover

In 2020, Cadence + TSMC + Microsoft focused on reducing cost and shortening schedule for semiconductor signoff on typical-sized designs. In 2021, Cadence + TSMC + Microsoft re-joined efforts to address the problem of growing chip size and related cloud-based signoff methodologies. The test example is in N5 technology with 800M cells (so billions of transistors).

In detail, the webinar will look at:

• Using Tempus distributed across many cores/servers
• What types of Azure VMs are appropriate
• New Tempus machine-learning memory prediction tool enabling sizing of VMs
• Virtual private chambers, licenses, PDKs etc

New features for 2021 collaboration:

• TSMC advanced node technology applied to a very large design
• Latest Microsoft Azure cloud VMs designed for EDA workloads
• Latest Cadence CloudBurst Platform on the Microsoft Azure cloud
• Giga-scale cloud concept using Cadence Tempus Timing Signoff Solution

Summary

• Ready-to-use CloudBurst Platform on Microsoft Azure
  • TSMC-approved for VDE in cloud
  • Optimized for Tempus Timing Signoff Solution
  • Distributed STA using giga-scale cloud concept
  • Maximize TAT, efficiency, cost savings
  • Ideal for peak workloads – signoff, library characterization, regression, analysis
• With 175+ customers, Cadence Cloud Portfolio is proven
  • All-cloud, hybrid-cloud deployments
  • Fully managed cloud, no IT setup required

The Webinar

The webinar will be presented twice, once for US and Europe at 9:00am PST, 12:00pm EST, 6:00pm CET. There will be a live Q&A after the presentation. The second sitting will be 10:00am CST, 11:00am JST, 11:00am KST. There won't be a live Q&A (I assume a replay of the earlier Q&A).

Here is the event page, including a link to register. You will need to pick which of the two sessions you want to attend when you register.

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