Moore's Law Slowing? Don't Tell TSMC

TSMC is a manufacturing powerhouse. It has twice the capacity of any other non-memory semiconductor company. It has the best yield in the industry, driven by collecting over 1M datapoints per second from the equipment in its fabs. They are the only company that can ramp from a standing start to full volume by adding 20K wafers per month for three consecutive months. So from 0 to 60K wafers per month in a single quarter (basically manufacturing 90K wafers in the first quarter and then 180K wafers each quarter after that).

To support this, they spend $2.2B on R&D, but if you add in the R&D of their top 10 fabless customers, the whole ecosystem has closer to $20B in R&D.

TSMC's biggest fabs, which they call GIGAFABs, are in various stages of operation/construction. Note that what TSMC calls a "phase" is what everyone else considers a whole fab with a capacity of 50K-80K wafers per month.

• Fab 12 phase 6 is now operational, phase 7 newly completed ready for 10nm and 7nm (still a parking lot it appears, when the above photo was taken). This is the mother fab for process development
• Fab 14, the largest fab in south Taiwan. Phases 1-4 operational. Phases 5-6 for 16nm. Phase 7 nearly complete. Phases 8-10 planned for 5nm and beyond.
• Fab 15, new site in central Taiwan. Phases 1-4 28nm. Phases 5 and 6 are ready for 10nm ramp with equipment move-in in May.
• Nanjing (China) fab has been approved and TSMC is acquiring 93Ha of land (1.6km by 5.6km). Groundbreaking in June or July this year. HVM in 2H 2018. Will be built in several phases
• Overall from 2015 to 2016, TSMC expects to increase capacity by 10% (about 65% 300mm, the rest 200mm)
• There is a migration from N20 to 16FF+ and 16FFC, but the total has gone up by 3X since 2014 (20+16 combined)

TSMC feels they have perfected ramping new processes to high-volume manufacturing. 40nm was a very gradual ramp over many months, and 28nm was gradual (although faster than 40nm). 20nm was an unprecedentedly steep ramp. However, 16nm was even faster, just three months to full capacity. In 2016, the plans are to continue the N16 ramp to 300,000 wafers per quarter. The defect measure D0 is now a record low <0.06. Was 0.1 when production started. The ramp for N10 is planned to be slightly steeper still.

Another area of focus is cycle time. The goal is one day per layer (D/L). They are ahead of this with 28/20/16 already at 0.6D/L. TSMC actually met the 1D/L for 16nm within the first quarter of volume ramp.

It is worth emphasizing just how fast TSMC is rolling out processes and ramping them to volume:

• 16FF+ started ramping in Q3 2015 and ramped at an incremental 20,000 wafer per month for three months to get to 60,000 wafers per month
• 16FFC started ramping this quarter and so should be at 60,000 wafer per month by the end of Q2 or earlier (since the ramps only seem to get faster)
• 10FF starts ramping in 2H 2016 with a planned capacity of 200K wafers/quarter. Risk production is just about to start.
• 7FF qual is planned for Q1 2017 (two processes, high performance and mobile). Risk production March 2017. Ramp in Q2 or Q3.

That is an unbelievable rate of both process development and, more spectacularly, ramping up multiple fabs into high-volume manufacturing. Nobody introduces new process nodes at twice the rate of Moore's Law: 16nm in 2015, 10nm in 2016, and 7nm in 2017.

On the morning of the TSMC symposium, ARM and TSMC announced a multi-year agreement to work on getting ARM processors for the server market in 7nm. That hardly counts as a surprise, of course, but I think the highest performance ARM processors (presumably what they have in development now) in 7nm in mid-2017 could have very impressive performance.

Until this quarter, 16FF+ was the most advanced process (ignoring risk production and test chips). It was comparatively expensive. Of course, cost and price is the one thing that doesn't get talked about in public by any foundry. The old rule of thumb was that moving from one process generation to the next would get a density increase of 50% but the wafer cost would go up 15% leaving a cost saving on a per-transistor basis of 35%. With double patterning, for sure 20nm was not 35% cheaper than 28nm (that it was the same price seems excessively pessimistic though). However, since 16FF+ has the same BEOL and so roughly the same density, and a more complex FEOL, I wouldn't be surprised if 16FF+ is more expensive per transistor than 20nm (although much better transistors). This is clearly one motivation for the development of 16FFC with 10-20% cost saving getting it close to being back on track. It is only a slight exaggeration to say that 16FFC is half-node between 16FF+ and 10FF.

Two years later they will be at 7nm with a huge density advantage and either a big performance increase for the HP flavor of N7, or a huge power reduction for the mobile version of N7. If all goes to plan, that is something that has never been seen before.

And the present? Last year TSMC:

• Manufactured 8.8M 12" equivalent wafers (that's one wafer every four seconds)
• In nearly 9000 products, for 470 customers, adding one new customer per week

Previous: CDNLive, It's Only Two Weeks Away

Next: A Brief History of Cadence: the Post-Costello Years