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The DDR5 standard has not been finalized by JEDEC, and they are very strict about not allowing anyone to claim DDR5 compatibility until the standard is complete. That is expected sometime this summer. However, getting designs into silicon can't wait until the standard is final before getting started. In principle, anything could change in the standard at any time until it is released, but everyone knows that the basic parameters are not going to change at this late date. Almost exactly two years ago, Mellanox's Gilad Shainer said to me that "interoperability is the only way to prove standards compliance." He was talking about PCIe 4.0, a standard that hadn't been completed when we talked. But the same idea applies to next-generation DRAM.

Cadence 7nm Test Chip and Micron Interoperability

Cadence has created a test chip containing next-generation memory interface IP based on the discussions of what is likely to be in DDR5, and Micron has produced prototype DRAM chips. The test chip was fabricated in TSMC's 7nm process, and contains both the controller and PHY. The two chips work together successfully achieving 4400 megatransfers per second, 37.5% faster than the fastest commercially available DDR4 memory. As far as we can tell, this is the first demonstration of DDR5 IP working with memory chips.

I talked to Cadence's Marc Greenberg. He pointed out that DDR5 is mostly a capacity solution, more than performance. As die get bigger, they get slower, due to all sorts of laws of physics. As you start building a 16Gb die in 1X memory technology, the distances start to get really long, which changes a lot of core timing parameters for the worse. Then the memory can't keep up with the CPU and so has to be overdesigned, making it bigger still, and so on. But everyone wants more memory in each server, for bigger datasets, bigger databases, bigger netlists, and so on. Cloud companies charge people for the memory in their instances and so there is a direct line from memory capacity to revenue. The DDR5 standard is aimed at making 16Gb die easier and to make vertical stacking easier. The speed of the core is unchanged, but the I/O is higher speed.

DDR5 segments the memory in a slightly different way so internal core timing can return to more nominal values. However, with a 16Gb die, the weakest transistors out ouf 16 billion will be many sigma from the mean. There is provision for on-die ECC, which can correct errors in the weakest transistors. If you have a giant bell curve with 16-billion transistors, and you can fix the 10 worst-case transistors, this can improve yield substantially. Note that this is for the convenience of the memory supplier, by getting yield up. This doesn't avoid the need for system-level ECC.

DDR4 today is not up to its maximum speed. Mainstream parts today are 2400 megatransfers per second. The high end is 2667 (for example, look at what you get if you buy a Dell server). That will become mainstream this year, so we are still a couple of years from DDR4 reaching its maximum of 3200 megatransfers per second. DDR5 is expected to be 4400 megatransfers per second at first, which is what the Cadence test chip achieved. 6400 is the maximum but it will be many years before anyone gets there. As Marc kept emphasizing, DDR5 is more about capacity than performance. Memories "don't get faster very fast."

Recently I wrote about DDR5 channel analysis, since it will require DFE (decision feedback equalization). See my post AMI for DDR5 Made Easy. The reality is that the DRAM channel is pretty horrible. There is the CPU, which is usually in a socket rather than soldered to the board, then the PCB is mass produced and so has limited layers and not the highest end materials, there is some distance to go across the PCB since the DIMMs are 5" long and can't be put next to the CPU. There are multiple DIMM sockets, perhaps some empty. All of this makes for an ugly environment, with lots of reflected signals, which is why it doesn't get a whole lot faster. The DDR5 DIMMs are different from previous generations—the form factor is similar, but it is divided into two channels.

Micron also collaborated with Cadence to deliver the industry's first IBIS-AMI model for (provisional) DDR5 in early 2017. This was presented at DesignCon earlier this year.

DDR5 Summary

Once again with the caveat that the standard is not final, here is what it looks like DDR5 will specify:

• supply voltage will drop from 1.2V for DDR4 to 1.1V for DDR5
• data rates will run up to 6.4 Gbps eventually, 4.4Gbps initially
• on-die termination (pulled-up VDDQ) will be available for address buses, not just data buses

What's Next?

Cadence plans to be first again with IP for LPDDR5 and future generations of other memory standards such as HBM. I'm sure I'll be covering them when we are ready to announce.

The graph above shows the adoption of the different DDR, LPDDR, and HBM interfaces. One major trend is shown by the red line, which is the percentage of mobile DRAM, which is almost half the market already and expected to grow a little more.

More information about our DDR controllers is on the DDR IP page.

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