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One presentation at the recent CDNLive Silicon Valley was about using Cadence tools to design products on TSMC's N7 process (7nm). It was standing room only, even after moving to a bigger room. The focus of the presentation was on the digital flow and it was by Cadence's Rod Metcalfe and TSMC's Jason Chen.
Rod started with a bit of history. Innovus first appeared at 16nm where the big new challenges were FinFET and some colorization (due to multi-patterning). Then 10nm brought full coloring, second-generation FinFET. The other big change was the increase in wire resistance, which made layer selection for interconnect more important. 7nm is the third generation and it is a big change from an EDA perspective.
N7 is an important process, with many customers going straight from 16nm to 7nm, and with customers who really want N10 going to the new 12FFC instead. N7 is also expected to be a "long-lived" process like 28nm, with not just a long life of products shipping in volume, but with new designs being started for a long time. If 28nm is any guide, there will be variants of it produced over the years.
Synthesis is generally considered to be independent of the underlying process. Give it the library and the netlist and it does its thing. But that is not true at N7, since Genus synthesis and Innovus implementation share the same placer, and some of the N7 changes affect cell placement.
The initial focus of N7 is high-performance computing (HPC), and presumably high-end mobile. By definition, HPC is high frequency, often 3+GHz, meaning that IR drop and EM/thermal are big issues. You can attempt to drive a lot of current down a small wire.
One new feature of N7 is the via pillar. This means that to get between levels of interconnect it is not necessary to make little short runs on every layer on the way up or down. Instead, vias can be stacked on top of each other. However, there isn't enough current carrying capacity at the lowest levels and so multiple vias are requred. Generally, this feature is used in restricted ways and the via pillar is usually attached to the library pin—everywhere that cell is used it will have a via pillar, typically on the output. The above diagram is a vertical cross-section through a via pillar.
This, in turn, affects placement since the pillars are larger than the pin and it is not possible to just place two small cells with a via pillar right next to each other, which goes under the name of a "halo check", making sure the placement is legal. It also needs to be understood up in synthesis, since placement and layer assignment affect area and timing. However, since there are shared engines, a lot of this comes for free. Via pillars also use up some routing resources since routing on the intermediate layers has to stay clear, but since they are used sparingly, this is not, it seems, a big issue.
Another new feature at N7 is trim-aware routing. There are two ways to manufacture metal. The first is simply to put polygons on the metal mask and adhere to the relatively large spacing between the end of routes that this requires, and also adhere to the minimum metal area rules. The other is to place a continuous grid of metal and then use a separate cut mask to separate the routes, which allows the gap to be much smaller. This eventually needs to work its way through the entire flow and emerge as a separate mask, which also means that the rest of the flow needs to be trim aware.
Quantus is fully certified at N7 but there are some new capabilities. Incremental extraction allows ECO changes to be made without requiring a new full-chip extraction. Virtual metal fill allows the timing effects of metal fill to be taken into account without requiring all the individual polygons to be generated and extracted. There is capability to extract inductance.
Timing in N7 is non-Gaussian, meaning that extensions are required to LVF to get enough accuracy. This has been ratified by the liberty format board and so should be ready for N7 library characterization.
All these differences come together in clock tree synthesis (CTS), which needs to be via-pillar aware and variation aware.
Voltus handles IR/EM as usual, but adds statistical EM rules. Another big change is analysis of self heating, which is much more significant at N7 and so requires new capabilities.
N7 is fully supported by Pegasus, Cadence's new physical verification system. (See Test Flying Pegasus and Pegasus Flies to the Clouds.)
This is inevitably a whistle-stop tour of the N7 flow, glossing over a lot of details. The Cadence digital flow is ready for N7, and pipe-cleaner designs have already gone through.
Rod said he was surprised at how fast people are moving to N7, there are lots of projects going on (but he wasn't naming any names). Cadence's approach to developing new capabilities is to get the engines giving the right results first, and then worry about making it easy to use. But early users see all the warts and have to wrestle the tools to the ground with their bare hands. The final version will be a lot easier to use, although it is clear that N7 designs will be challenging with so many new aspects of the process showing through into the designers' world.