TSMC OIP: N3, N4, and PCIe 6.0

Next week is TSMC OIP 2021 (or, to give it its full name, TSMC 2021 Online Open Innovation Platform (OIP) Ecosystem Forum). I will be attending and so you can expect a few blog posts covering the material presented in the coming week or two.

In the meantime, today Cadence made two TSMC-related announcements.

TSMC N3/N4 Certification

The title of this press release, Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certification, is pretty self-explanatory. About once a year, we put out a release like this and only the process node changes. Really this is just adding the latest nodes to the general statement that the entire Cadence tool portfolio supports and is certified on all TSMC processes.

Although this announcement groups N3 and N4, these are actually from two different process families. N4 is the optical shrink of N5 with the same design rules. N3 is the first generation of TSMC's new process family. N3 will continue to use FinFET transistor structure. Beyond 3nm, TSMC says they have made major breakthroughs in nanosheet devices, which offer short channel controls presenting opportunities to achieve good performance at lower voltage. TSMC expects to use design and technology co-optimization to increase nanosheet performance by a double-digit percentage

PCIe 6.0

We also announced a working testchip for PCIe 6.0 built on TSMC's N5 process. For more details on PCIe 6.0, see my post The History of PCIe: Getting to Version 6. There is a big difference between PCIe 6.0 and earlier generations since the signal encoding has switched from NRZ (one bit per clock cycle) to PAM4 (two bits per clock cycle). Note that the PCIe 6.0 standard has not been finally approved (it is at version 0.7 now) although no significant changes are expected at this point.

The 5nm PCIe 6.0 PHY test chip silicon demonstrated excellent electrical performance across all PCIe rates. The PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry, and linearity with extremely low jitter. The DSP-based receiver demonstrated robust data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64GT/s. In addition, the advanced DSP core in the PHY provides continuous background adaptation to monitor and compensate for the signal fluctuations induced by environmental factors, achieving enhanced reliability.

The controller IP for PCIe 6.0 is designed to provide the highest link throughput and utilization while operating with extremely low latency. The highly scalable multi-packet processing architecture supports up to 1024-bit wide data path in x16 configuration while operating at 1GHz to achieve maximum aggregate bandwidth of 128Gbps. The feature-rich controller IP supports all the new PCIe 6.0 features, including PAM4 signaling, Forward Error Correction (FEC), FLIT Encoding and L0p power state while retaining full backward compatibility.

Watch a demo of PCIe 5.0 and PCIe 6.0 (7 minutes):

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