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Last Wednesday was the TSMC OIP Ecosystem Forum. The first part of the day was hosted by Dave Keller, President of TSMC America. He pointed out that it was the 10th anniversary of OIP. It has been a great success ensuring that EDA and IP are ready for customer designs. He talked a little about OIP in the cloud—"only the sky is the limit"—which I covered that morning in my post TSMC OIP Virtual Design Environment.
But probably what most of you readers of this post really want to know is what was said about process and ecosystem roadmaps. Cliff Hou gave the keynote with all the information. Once again I will give my caveat that TSMC does not allow photography, video, audio recording, and they don't hand out the presentations. So this is completely based on my notes.
On Reddit, long posts often have a summary at the end that is indicated with TL;DR, such as "TL;DR a diet of only grapefruit is not advised". It stands for "too long, didn't read." But I'll be nice and put it at the beginning, in case you don't want all the details. Cliff's summary was:
Or "the cloud thing" as Cliff called it. Since 2008 OIP has been about IP, EDA, DCA, VCA...and now the cloud too. VDE is basically current design flows in the cloud: tool settings, interactive responsiveness, CPU/memory configurations, and license management. If you want to use Cadence tools (and why would you not?) then Cadence is the one-stop storefront.
Cliff said that TSMC themselves have rapidly adopted cloud usage internally for N5 SRAM development. The schedule was pulled in with more CPUs, the quality was better due to the larger number of simulations that they could run in a shorter time. For high utilization they use in-house (on-prem is the buzzword) datacenters, for surge they used the cloud.
N5 is ready for design starts. EDA V0.5 certification is done, with V0.9 ongoing (to be complete in November). Foundation IP (standard cells, SRAM, GPIO, eFuse) all have early silicon validation results. Interface IP in development.
TSMC built an Arm A72 core implementation as a test vehicle, getting a 15-18% area reduction at the same power, or 1.8X logic density (the number varies depending on whether the design is wire-dominated or gate-dominated).
N7 EDA is all fully validated and deployed. Foundation and ecosystem IP fully silicon validated and deployed.
Cliff didn't say it, but my understanding is that N7+ is basically N7 with EUV inserted, allowing for CPODE (continuous poly on diffusion edge) and tighter metal pitch. There is also a 1-fin cell library. The PPA is 1.2X denser logic (compared to N7, meaning N7 is 1.2X the size of N7+ I believe) and 6-12% power reduction (I think in this case it really does mean both at the same time, denser and lower power).
N7+ foundation IP is silicon validated. EDA v1.0 certification is completed and deployed to leading customers. In fact the first tapeouts happened already in Q3. The one piece that is still in development is OTP, but everything else is ready and validated.
N22 processes are a 5% optical shrink from 28nm...yeah, that means it should really be 27nm. It has new photoresist and a new litho/etch integration. These two processes have enhanced RF, AVT device for better analog design, eMRAM and RRAM. There is an automotive service package. ULL (ultra-low-leakage) has 0.6Vdd operation and improved transistors.
The reason for having two low-power 22nm technologies is that the application band is very wide. 22ULP has device optimized for performance but for low-power applications like Bluetooth LE and automotive there is ULL with ultra-low leakage. There is strong demand for <0.6V for BLE and low-power MCU. Overall there is a 3X power reduction from 40ULP.
In terms of enablement, V0.9 is ready, 1.1 is August 18 (for 0.8V and 0.9V) and V1.1 in April 2019 for the extended voltage range from 0.54V to 1.05V. The 0.6V standard cell libraries will be available June 2019.
16FFC is in production. Everything is ready.
TSMC is extending the full platform to N7. Most items already passed and available. SER and PERC Q4 2018. Interface IP certification mostly Q4 2018 with some in Q1 2019. Today it is already being used by early N7 automotive customers.
3D WLCSP for smart sensor (put the sensor on top of the logic die, as has been done with image sensors for many years).
InFO on Substrate (InFO_oS) technology. This is a chip-first solution enabling better scalability. 2um SoC to Soc interconnected, min 40um SoC I/O pitch and in 130um C4 Cu bump pitch. All qualified on 1X reticle size with product ramp in 2H 2018. There will be a 1.5X reticle size for larger systems.
InFO with Memory on Substrate (InFO_MS). This is SoC+HBM integration (on a substrate, not with HBM on top of logic). 1X reticle size (830mm2). Qualification is done for 1X reticle size, ready for production end of 2018. It has fine pitch with Cu RDL routing at 2um/2um.
CoWoS. In 2017 had 1.75X reticle size, and next year moving to 2X reticle size (by Q1 next year). Alternatively (but not at the same time, at least yet) C4 bump pitch is reducing from 180um to 130um, available at the end of 2018.
All those technologies are in production with some incremental development going on. The new technology is System on Integrated Chips (SoIC). This involves innovative stacking of multiple chips with very fine pitch (<10um) chip-on-wafer bonding process (CoW). It is compatible with many package types using flip-chip accepting bumps. This is a bit hard to explain since I don't have TSMC's diagram, but the technology has chip1 with chip2 on top, with bumps on top of the stack (back of chip2) accessed by TSVs through the top chip. Alternatively, there can be chip1 on the bottom, and more than one chip on top, flipped over with a CoW bond in the middle, and bumps on the top reached by TSV through the top chips. SoIC will have the technology ready in Q1 2019 and in early April "we will be ready".
I gave you the summary at the start, but here it is again:
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