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Last Monday it was the TSMC Technology Symposium, held virtually of course. Today, I'm going to cover a little bit on the opening, but then focus on advanced digital processes (presented by YJ Mill) and manufacturing excellence (presented by YP Chin). At a future date, I'll cover the presentations on specialty technology (presented by Kevin Zhang) and advanced packaging (presented by Doug Yu).
Dave Keller, President and CEO of TSMC North America, was the opening host, as usual. He showed that there were over 2000 people attending online. It might have been quite a bit higher, since anyone who was more than about five minutes late to the start of the symposium would not have been on.
He introduced TSMC CEO CC Wei who talked about the digital transformation. "With our world-class technology and your cutting-edge innovation, we can achieve more together". I won't go into a lot of detail on what he said, since much of it was repeated with more color in the other presentations. One important thing he pointed out is that N3 (which is a FinFET process) has risk production planned for 2021, with volume production 2H 2022. And TSMC is working with customers to define the next node after N3.
Note: In any discussion of processes, TSMC says things like "15% performance increase and 30% power decrease". This means either 15% performance increase at constant power, or a 30% power decrease at constant performance. You can obviously blend these and take some of the improvement in performance and some in power. But you don't actually get both of them at the maximum value simultaneously.
YJ had some pictures of the new R&D center that TSMC is building near their HQ in Hsinchu. It has a large office building that can house over 8,000 researchers and scientists, and two research fabs, R1 and R2. YP Chin filled in more detail in his presentation later.
First N7: there has been rapid and strong adoption of N7 with well over 1 billion working chips shipped to date. There are over 140 new tapeouts and will be over 200 by year-end.
N6 is a shrink of N7 using more EUV lithography. It has 18% logic density improvement. It also provides substantial cost saving over N7. It is pure shrink so is compatible with N7.
N5 offers 15% speed increase or 30% power reduction, and 1.8X logic density increase (versus N7). Its yield improvement (D0 performance) is even faster than N7 was. N5P offers a further 5% performance increase or 10% power reduction (but no change in area since it is the same design rules).
N4 (since this was billed as "Introducing N4" I think this was the first public discussion of the node) is a shrink of N5. It has performance, power, and density improvements (and a reduction in mask count) but YJ didn't say how much. Risk production is 4Q 2021 with volume production in 2022.
N3 is "the most advanced logic technology in the world". It is still a FinFET process. It will have a 10-15% speed improvement (versus N5), 25-30% power reduction, 1.7X increase in logic density, 1.2X increase in SRAM density, and 1.1X increase in analog density. Risk production is planned for 2021 with volume production in 2022.
He then moved on to "beyond N3".
First, they have new transistor structure (nanosheet) and new materials such as high mobility channel, 2D, carbon nanotube (CNT). TSMC has already demonstrated at 32Mb nanosheet SRAM fully-functional at 0.46V. It has also identified promising 2D materials such as MoS2 (molybdenum disulfide). At IEDM last year, they disclosed the first BEOL CNT power-gating device integrated with silicon-based CMOS.
Scaling continues with EUV advances with the current generation of scanners. They are also working with ASML (the only supplier of EUV equipment) on High-NA EUV.
There are improvements in interconnect RC with:
So those are the hints about what will be in N2, as it appears to be called (although that might just be what movie producers call a "working title").
He started with N7 capacity growth and N5 planned capacity growth. N7 is already 3.5X bigger than it was just two years ago, 28% CAGR. N5 has a similar ramp from this year to over 3X this year in 2022. YP pointed out that TSMC has 50% of the entire world's EUV installed base (number of scanners) but it has over 60% of the cumulative EUV wafer moves.
Next YP moved on to specialty technologies. In 2015, 38% of TSMC's capacity above 28nm was specialty technologies and it is expected to be 54% this year. Each year, TSMC invests over $10B to expand specialty technology. A couple of years ago at a TSMC event, it was pointed out that TSMC has never closed a fab. They just convert them to specialty technology that can be run on that generation of equipment.
Next, fab new construction status, starting with the Tainan site (southern Taiwan). F18 phase 1 and phase 2 are in volume production with P3 and P4 under construction. Also, to be constructed is F14 P8. Finally, there is fab AP2C which is under construction for advanced packaging.
Then the Hsinchu site. You can see the new office and research fabs R1 and R2 in the middle (R1 is under construction, R2 is planned). Down in the lower left, you can see four phases of a new fab planned for N2. TSMC is currently working on "land acquisition".
YP went on to talk about lowering TSMC's ecological footprint. They have created a wastewater recycling plant that can take greywater from outside and purify it to the levels required for semiconductor manufacture. Another development is that the fabs create a lot of water with copper residue in it, which they used to send out. Now they use electrolysis to create copper tubes, melt them into ingots, and then use them as targets for creating copper interconnect.
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