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This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president of TSMC North America was the MC for the day.
Dave kicked off by giving a few statistics about TSMC's business in North America. In Q4 last year, North America was 71% of TSMC's global revenue. The region consumed 6.1M 12" wafers (or equivalent—since it works by area an 8" wafer is half a 12" wafer, and a 6" wafer is a quarter).
Dave introduced CC Wei who is currently co-CEO of TSMC (the other co-CEO being Mark Liu). He is in transition to being the full CEO. This was all announced along with Morris Chang's full retirement to take place at the annual shareholders meeting in June this year. At that point, Mark Liu will become chairman of the board, and CC Wei will become CEO. Morris will no longer be on the board, nor have any role in management. I will cover his keynote along with the fab construction and ramps in a later post. I will just say, since it is a theme that ran through the whole day, that TSMC sees the two big trends that drive everything as being 5G and AI. Obviously mobile, but also automotive, IoT, and HPC, which are the four focus areas that TSMC has talked about for a couple of years now.
All through this post, you will see comparisons of processes by speed and power. If I say that a process is 10% faster, 35% less power then that means either you can take the improvement as performance, or you can take the improvement as power-saving, or as some mixture of the two. But you don't get to have the full 10% increase in performance at the same time as 35% less power.
YJ is the head of what is usually just called TD, technology development. This means semiconductor process technology development. It seems to be obligatory to have a very short name to head up TD—when I was at VLSI Technology our head of TD was Ho Yu, and it's hard to have fewer than 4 characters in your first and last names together.
YJ said he would talk about 5 subtopics: N7, N7+, N5, EUV, and research.
N7 is, of course, the first generation of TSMC's 7nm process. YJ said that it has passed all qualification, is in volume production now, with over 50 tapeouts planned by the end of the year, roughly a third in mobile, 2/3 in HPC, and a couple of automotive.
Compared to 16FF+ it has a speed increase of 35%, a power decrease of 65%, a routed gate density 3.3X higher, and SRAM cell size 0.37X.
N7+ is a further density boost, with 20% logic density improvement and 10% power reduction. This comes about since N7+ uses EUV for some layers. More details on EUV came later in YJ's presentation. N7+ is already demonstrating the same SRAM yield as N7, and has passed all wafer reliability checks. Customer product tapeouts are expected in 2H 2018 with risk production starting in Q3.
N5 will be the best technology in 2019 "further extending TSMC's technology leadership". Compared to N7, it is 15% faster with the normal transistor, or up to 25% faster with a new ELVT transistor (Extremely Low Voltage Threshold). Power is reduced by 30%. Logic density is increased by 1.8X. It is a full-fledged EUV process, not manufacturable by immersion, with 30% fewer masks than N7.
The 256Mb SRAM yield has already reached double digits (without repair), which is ahead of schedule.
Risk production for 5nm is planned in 1H 2019 primarily for HPC (and high-end mobile).
TSMC are very confident to deliver EUV for high-volume manufacturing in 2019. There are multiple EUV layers implemented in both N7+ and N5. They are continuing aggressive installation of NX3400 steppers (the current state-of-the-art ASML product) for volume production.
TSMC is running the light source at 145W in daily operation since the start of the year. They demonstrated 250W just two weeks before in April. This is a huge milestone, since for several years everyone has said that a 250W light source is necessary for volume manufacturing, since otherwise the wafer throughput is too slow. The other aspect of throughput is the sensitivity of the resist. TSMC has significantly reduced resist dosage and is on-target for 1Q19 production schedule.
Another EUV challenge has been pellicle transmission. Without a pellicle on the mask, any contamination risks messing up a lot of wafers before it is detected and cleaned. The pellicle is more complex with EUV for two reasons. First, since it is reflective optics, the light path goes through the pellicle twice. Second, the 13.5nm EUV light is absorbed by almost everything (even air, which is why an EUV stepper is in a high vacuum) and so there are not very many materials that are practical. YJ said that they now have pellicle transmission at 83% with a target of 90% in 2019.
Once the EUV lithography is used to create structures, it has better process control (smaller variation), better CD uniformity, and better pattern fidelity. They are getting good yields in both N7+ and N5 with multiple EUV layers. A single pattern EUV can replace 4 immersion litho layers.
Beyond FinFET, TSMC is looking at nanowires, in particular stacked horizontal nanowires. YJ had a micrograph of a gate with 8 separate wires running through the gate. There is also the opportunity to go to nanosheets, where the wires are elliptical not circular, which makes it possible to fine-tune the device widths. This is important technology for pushing transistor scaling to 2nm and beyond.
Then, beyond silicon itself, is Ge (germanium). Germanium enables lower power at the same performance compared to a silicon transistor. They demonstrated for the first time Ge CMOS-compatible gate-dielectric and world-record low contact resistance. A TEM image showed the capability to produce Ge nanowires.
Future transistors might exploit 2D material. These exhibit high mobilities down to sub-nm thickness. For regular materials, line-edge-roughness (LER) is an increasing problem. What currently seems an attractive 2D material is MoS2 (molybdenum di-sulphide) which has good carrier mobility down to the nanometer range.
For interconnect, they are looking to extend copper with giant grains. YJ showed a cross section with Cu grain 10X normal size. This can reduce metal resistance by more than 50%. They can also do selective dielectric-on-dielectric (DoD) deposition, enabling full self-aligned Cu vias to increase reliability, and a 50% improved via-to-line breakdown voltage.
TSMC have several processes that go under the ULP (ultra-low-power) naming, and also ULL that extends the ULP process with ultra-low-leakage transistors. For the advanced (post 28nm) nodes, there is N22 ULP and ULL with a wide range for adaptive voltage scaling from 0.9V to 0.6V. He showed a graph of a design at 90LPP using 35 units of power (presumably not watts!) at 1.2V, going to 40ULP at 0.7V where the units went down to 10, and then to 22ULL at 0.6V cutting power to 3 units, so from 90 to 22, a 90+% power reduction.
The ULP technology will be extended to 12FFC_ULL using a low-power FinFET. Note that 12FFC is an optical shrink of 16FFC, so is a sort of half-node between 16 and 7.
In emerging memory, they are looking at all three of MRAM, RRAM, and PCRAM (magnetic, resistive, and phase-change). These are all built in the back-end (in the metal stack). I will say more about memory when I cover the afternoon sessions, since there was more detail of what will be available when.
Of course, flash is not completely forgotten. They have the leading 28nm eFlash for high-end Grade-0 applications, built on top of 28HPC+. Grade-1 qual is planned to complete in 1H 2019, and Grade-0 qual in 2H 2020.
Both RRAM and MRAM have made great progress. 40RRAM is ready for production, as a flash alternative for IoT. It has completed qual. Unlike adding flash, it is just two extra masks.
22MRAM will be ready in December 2018 as an eFlash alternative for mobile, HPC and automotive. It has superior performance to eFlash, with 3X faster write, 10 years retention after a million cycles at 150°C.
TSMC has been in MEMS for several years, starting in 2016 with a motion sensor (over 350M units shipped), then in 2017 with a capacitative pressure sensor. In Q3 2018 they will have a WLCSP sensor SoC.
TSMC is focusing on GaN (gallium nitride) as opposed to SiC (silicon-carbide). YJ said they have "GaN on silicon leadership" with GaN power 100V and 650V driver integration by 3Q 2017 with better performance, smaller form factor, and more effective power control.
They also have GaN RF with a 30V D-MISFET qualified for RF switching in 2017, 100V D-HEMT to be qualified in 2019 for 4G/5G RF power amplifiers.
There was a lot more discussion on advanced packaging in the special session in the afternoon. But YJ's summary was that:
CoWoS is moving to larger interposers and finer Cu bump pitch to house more functionality and performance. CoWoS with 1X reticle size and 130um bump pitch will be in production later this year, going to a 2X reticle size interposer in 2019.
There is also innovation going on in the InFO and chip-level 3D IC solutions to enable heterogeneous integration with small form factors for mobile, IoT and HPC. In particular InFO_MS (memory on substrate) on a 1X reticle size fanout with 2um RDL interconnect. This will be qualled by end of 2018.
For mobile, there is InFO PoP with or without backside RDL and optional BSFDL to match DRAM package footprint (over the top of the SOC) and including integrated passive devices (IPD) for better performance.
Multi-stacking got its own acronym MUST (MUlti-layer-STacking). This is TSV-free 3D stacking for small form-factor and enhanced performance. You can have an SoC on the bottom, with one or more on top, and TIV going down around the base SoC for connections, without any TSVs going through the base die.
For radios, there is also InFO_AIP (antenna-in-package) with two different types of antennas available depending on whether it is millimetre-wave or lower frequency.
Finally, YJ introduced SoIC (system-on-integrated-chips). This has innovative stacking of multi-chips with very fine pitch (10um) using a wafer bonding process. I think that this is a superset of the WoW technology that I wrote about earlier in the week (see WoW! TSMC Sticks Whole Wafers Together). It is compatible with many package types such as flipchip, InFO and CoWoS. He showed one picture that had two chips of identical size like in my earlier post, but also one with two small chips on a larger chip (which obviously cannot be done with two whole wafers).
Coming up, status of fabs and product ramps. Details of mobile and HPC, IoT, automotive. More on advanced packaging.
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