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Earlier this week it was the TSMC Technology Symposium. Here's my first post, summarizing TSMC's technology roadmap. As I do every year, I start with the caveat that this is all done from my notes, recording and photography is banned, and they don't hand out any slides. I was the guy typing like a madman at the front of the auditorium (they had reserved seats for media, which makes it a little less hectic).
CC Wei, TSMC's CEO was up first. I'll leave out the process stuff since it was covered in more detail later. This was the 25th Technology Symposium (the first had 100 attendees).
Fab 16 in Nanjing is completed and running 16nm.
Fab 18 in Southern Taiwan Tainan City is for 5nm and below. Construction is complete, and equipment move-in has started. Risk production of 5nm will begin there in Q2 2020.
In 2018, TSMC's total capacity was 1M 12" wafers per month. They did over 12M with "the best cycle time and yields industry-wide". They also delivered 11M 8" wafers, too, which has been rising at a 14.3% CAGR over the last five years.
This section is based on Yuh-Jier Mii, who runs technology development. I'm not going to talk about anything above N7 (7nm, although TSMC uses the Nx terminology for the advanced processes).
N7+, the second-generation 7nm process is in production with yield the same as N7. The volume ramp that TSMC executed for N7 was the fastest ever to meet time to market, faster than 10nm and 16nm. It also has the steepest yield learning curve, d0 coming down faster than in previous nodes. The volume ramp for N7+ will be in 2H 2019.
The difference between N7 and N7+ is the use of EUV. They have made improvements in EUV power and tool availability for volume. Now up to 280 watts, on track for 300W this year and 350W planned for 2020. They have achieved 85% availability, up from 70% in 2019, and plan for 90% in 2020.
There is a new process, N6, which makes more use of EUV to reduce process complexity, and improve yield. The die area has an 18% logic density gain. The design rules are backward compatible, so are SPICE rules, and IP. Same tool flow. During his earlier presentation, CC Wei said that N6 will be in risk production in the fourth quarter next year. I suspect that should maybe be this year since they already have N5 in risk production.
The next process is N5 and N5P. Risk production started in March 2019 (last month) on schedule. It gives a speed up by 15% or power reduction by 30%. 1.8X logic density gain. Obviously, it uses more EUV layers. N5P is a performance-enhanced version of N5 planned to be ready in 2020, giving a further speed boost of 7% and power reduction by 15%. It will have the same design rules as N5 (different SPICE models obviously). N5 are the first fully strained high mobility FinFETs in production, with high on-state current.
The next nodes on the roadmap, albeit in grey, are N3 and N2.
TSMC is at the exploratory research phase to see "how long we can continue scaling." We can continue for now. Since TSMC was founded, logic density has improved more than 10,000 times. The first phase of scaling was the Denard era, which ended around 2000 when the threshold voltage hit its limit. Then new materials but still a planar process until optical lithography hit its limit. Now it's "more new materials, planar to FinFET, a lot of DTCO, EUV, high mobility channel."
They are now looking at new transistors and new transistor material, and gate all around (GAA). He had a photo of stacked nanosheet transistors with 5 nanowires. Germanium channel. There are also some promising 2D materials since mobility will be degraded at 1nm and below. Sulfides and selenides have been identified as promising materials, showing higher on-state current that a silicon transistor at 7nm. WS2, MoS2, WSe2.
They are extending interconnect scaling with a graphene cap on the copper, which reduces line resistance by 15%. Also they are working on new low-k material since the current ones are susceptible to process damage.
Beyond that interconnect moves beyond copper damascene. They have formed metal lines at a pitch under 30nm with near vertical profile.
Finally, Yuh-Jier got to advanced packaging. All the 3D packaging technologies have complex acronyms. CoWoS is the oldest technology, for chip-on-wafer-on-substrate. InFO stands for integrated fanout and is a cheaper technology, and comes in several flavors. SoIC (which I think stands for System on Integrated Chips) is the newest technology.
They have already been through three generations of CoWoS, InFO_Pop, InFO_oS, InFO_MS. Now the SoIC (chip on wafer) and WoW (wafer on wafer) that were announced last year. They are ramping CoWoS with 130um and will extend to 2X reticle size in 2020 with five metal layers and deep trench capacitors for better power and signal integrity.
They are extending InFO to high-performance computing. InFO_oS integrating two SoC chips side by side. Production started last year. Also, InFO_S with memory on substrate alongside. SoIC and WoW can both support face to face, and face to back. But there is no limit on die size. Can stack different sized dies (well, not for WoW).
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