TSMC Technology Roadmap, 2023 Version

April brings one of the two times during the year that TSMC lays out its process roadmap, fab construction plans, and more at the TSMC Technology Symposium. The other is the Open Innovation Platform Ecosystem Forum in October, usually just referred to as "OIP."

Dave Keller

As usual, the day opened with Dave Keller, CEO of TSMC North America. He set the scene and gave some statistics on TSMC's North American business.

I don't think it was a surprise to the sort of person that reads Breakfast Bytes, but during the pandemic, many people (CEOs of automotive companies, politicians) found out how essential the chip industry is to everyday life. Estimates are that the semiconductor shortage cost the US $240B in 2021 and caused a dip of 8% in automobile sales in 2022. It is almost certainly a contributor to the fact that there is $52B for semiconductors in the US CHIPS and Science Act.

Another big development over the last few years has been the growth in artificial intelligence (AI). The growth in AI has been especially dramatic in just the last few months. ChatGPT is the fastest growing thing ever, acquiring 1M users in five days and 100M in a few months. Dave likened it to some of the biggest transitions that society has been through: fire, steam, electricity, the internet, the smartphone...and now AI.

CC Wei

Next up was Dr. Wei, TSMC's CEO. He echoed some of Dave's remarks:

The world runs on semiconductors.

He talked about some of the macro challenges. First, the pandemic. Then geopolitical tension. Then the Ukraine war. All of these increased costs.

Moore's Law is another challenge in the sense of keeping semiconductor scaling on track. But it is not the only factor. 3D-IC (or 3DFabric in TSMC-speak) improves the system performance, so in that sense is still Moore's Law.

CC introduced a couple of guest speakers from Qualcomm and Analog Devices, but in the interest of space, I'm not going to attempt to summarize what they said. Let's get onto the details and roadmaps.

Cliff Hou

Next up was Cliff Hou, SVP of Corporate Research and Europe and Asia Sales, who presented Market Update and Outlook.

By 2030, the global semiconductor market will be about $1T. His prediction is that the split will be 40% HPC, 30% mobile, 15% automotive, 10% IoT, and 5% other.

The TSMC N5 has been in volume production since 2020 (the first foundry to start volume production of N5). They have continued to enhance that process with N4 (optical shrink, I think), N4P (power efficiency), N4X (high performance), and N5A (automotive).

The TSMC N3 entered volume production last year, the first in the semiconductor industry to reach high-volume production with a good yield. The mainstream 3nm process, N3E, will be in production during the second half of this year. For the first three years since inception, the number of new tapeouts for N3 and N3E is 1.5 to 2X that of N5 over the same period (over the first three years). There will also be N3P, N3X, and N3A variants. I'm not sure anyone mentioned it explicitly, but N3 is a FinFET process.

N2 (nanosheet transistors, or more generically gate-all-around or GAA) is on track for production in 2025, bringing the best performance, cost, and technology maturity.

Energy efficiency has been growing at a CAGR of 15% over the 10 years from 2015 to 2025, which is N10 to N2.

There are many 3DIC package solutions to boost system performance (see later in this post). TSMC has built 500B transistor systems with 100B transistor die.

Specialty technology is increasingly important: RF, CIS, PMIC, NVM, ULP, Auto (key: RF=radios, CIS=image sensors, PMIC=power management, NVM=non-volatile memory, ULP=ultra low power, auto=automotive).

Here are a few process names:

RF: N6RF, N6RF+, N4PRF (coming). Many customer tapeouts last year.

ULP: N22, N12e, N6e (coming).

NVM: 28/22nm (embedded flash), 16/12nm, and 6nm with MRAM, and RRAM. More on this later.

Auto: N7A, N5A (qualified), N3AE, N4AE, N3A. AE stands for "auto early" and allows design groups to start designs in anticipation of the fully qualified automotive process N3A which will be qualified by 2025. It will be the world's most advanced technology for automotive products.

He talked a little about fabs and TSMC's global manufacturing footprint. In Taiwan, Fab 18 (in Tainan, the main base for N3), Fab 20 (in Hsinchu), and Fab 22.

Ecosystem readiness. EDA, IP, DCA/VCA. Also partnerships with memory, substrate, testing, and OSAT. Today 55,000 IP, 3000 technology files, and close to 3000 PDKs.

3DFabric alliance, with 20 partners (including Cadence).

Global manufacturing footprint. First, Taiwan is home to Fab 18 (in Tainan, base for N3), Fab 20 (Hsinchu), and Fab 22 (Kaohsiung).

Then there is Fab 21 in Arizona, which is the biggest foreign direct investment in Arizona's history. Phase 1 is for N4 production starting at the end of 2024. Construction has already started on phase 2, which will be N3. The combined capacity when complete, will be 600,000 wafers per year.

Fab 16 in Nanjing (China) for 28nm has started production.

Fab 23 is JASM (Japan Advanced Semiconductor Manufacturing), a joint venture with Sony and Denso. Volume production is planned for the end of 2024 for CIS and microcontrollers. The fab is in Kumamoto, also where my favorite oysters originated.

Fab 21 in Arizona. Largest foreign direct investment in Arizona history. Phase 1 is for N4 production starting end of 2024. Also started construction on phase 2 for N3. Combined capacity 600,000 wafers per year.

Next, a little about sustainability. By 2030, TSMC’s tap water consumption per unit of production will be reduced to 60% of 2020 level. It has already built a water reclamation plant in Tainan and will build one in Hsinchu in 2025. The plan is to build an industrial water reclamation plant in Arizona, too (as you probably know, Arizona is not noted for its wetness).

YJ Mii

Next up was YJ Mii, the SVP of Research and Development on Advanced Technology Leadership.

They are accelerating investment in R&D to $5.47B this year. The advanced technology roadmap is really split into two streams, the high end for premium mobile, data center, AI, and ADAS/autonomy (that's the top row in the diagram above). The lower row is mainstream for more price-sensitive markets such as mid-level and low-level mobile, consumer, base stations, and networking.

N7, N7+, N5, N5P, N7A, N4, N3 are all in production. N3E will be in production this year. N5A will be 2025 (although it shows as. 2024 on the table above). N3A, N2P, and N2X will be 2026.

N3E production is on schedule. N3E vs. N5 V1.2 has an 18% performance gain or 32% power reduction, 1.6X logic density, chip density (presumably memory didn't shrink as much) 1.3X increase in density. TSMC will then introduce N3X (additional Fmax gain) and N3P (with much lower leakage).

N3AE (auto early) can be used starting in 2025 and go into production in 2026 when the technology is available and qualified.

N2 development is on track. Nanosheet device performance is over 80% (I think that means TSMC feels that it is 80% done on what needs to be done for logic transistors), 256Mb SRAM testchip now yields over 50%. N2 offers a 13% speed gain or 30% power reduction (presumably versus N3E).

N2 will also have the option of backside power delivery network (TSMC says power delivery rail, but usually this is PDN when abbreviated), which results in a 10-12% speed increase and a 10-15% smaller logic area (but is obviously more expensive). It will be available 2H2025.

Beyond N2, TSMC is investigating novel devices, new materials, and continued scaling. CFET (stacking the N -transistor on top of the P-transistor) is a likely scaling approach, offering a 1.5X to 2X increase in density.

TSMC is also doing research beyond silicon. 2D materials (2DNSFET) and carbon nanotubes (CNTFET). There is a paper already submitted to VLSI 2023 on a demonstration of a transistor with 3D-material channel (it seems to be MoS2).

Work is going on on a new low-R barrier for Cu interconnect. That can provide a 20% reduction in via resistance and 15% in interconnect resistance.

For 3DFabric Technology, TSMC is adding microbump SoIC-P in addition to SoIC-X (existing bumpless tech). CoWoS: CoWoS-S silicon interposer, CoWoS-L/R with RDL interposer. InFO PoP, Info-3 2.5D, InFO-3D.

CoWos 1.4 reticle today, 3.3 times next (and 8HBMstacks), 4xreticle, and 12 HBM stack after that. I didn't manage to write down the years.

3D silicon stacking technology. SoIC-P CoW, 18-25um pitch

SoIC-X CoW (chip on wafer) 4.5-9um pitch, also WoW version with bump pitch less than 3um.

Kevin Zhang

Next was Kevin Zhang, SVP of Business Development. He would reappear later to present to us press and analysts during the invitation-only lunch. Kevin was focused on Specialty Technology Leadership. One of the things that someone said during a previous Technology Symposium (maybe even Kevin) was that TSMC has never closed a fab. Obviously, as the leading edge moves on, the older nodes become "mature" by definition. But TSMC also invests in new variations on those processes too. In fact, TSMC's investment in specialty technology has grown (over the last 5 years) at a CAGR of 40%. For the first time ever, it is investing in building mature technology capacity and will expand by 1.5X over the next three years (this counts the TSMC/Sony/Denso fab in Kumamoto, Japan, which is all mature technology).

• ULP solution. 55ULP, 40ULP, 22ULL (0.6-1V) N12e (0.45-1V), N6e. 
• RF connectivity. N6RF offers fast er performance with 49% power consumption reduction compared to 16FFC enhancement (benchmark half analog, half digital).
• N4PRF most advanced RF CMOS technology. RF on top of logic for digital-intensive RF products. N4PRF vs N6RF logic density 1.77X, power reduction 45%
• MCU is all about how to scale non-volatile memory. MRAM and RRAM in 28nm/22nm since 2019. 16/12nmsince 2022, and 6nm in planning.
• 40RRAM And 28/22RRAM in volume production
• 28RRAM achieves >10 years 125° retention (automotive grade)
• 12RRAM to be released in 1Q2024
• 22MRAM in production
• 16MRAM consumer qualified in 2022, planned for automotive 2023.
• Achieve >1M endurance cycle, 20 years 230 degrees retention.
• Power management. Smart power IC drives BCD scaling.
  • N90 BCD+ since 2021.
  • N55 BCD+ SoI (pathfinding for automotive)
  • N50BCD+ with RRAM
• CMOS image sensor.  Resolution 50MP and beyond. Pixel size 11-1.4um. ISP (processor) N40 going to 12FFC.
• Roadmap for CIS has two logic layers with advanced packaging. Allows for AI in the logic.

 YP Chin

Next was YP Chin, SVP of Operations, with TSMC Manufacturing Update. 

Advanced technology capacity has a 2019 to 2023 CAGR over 40%. Specialty technology 12” capacity growth CAGR 10% 2019-2023.

Big chips in advanced technology are growing fast. Chips with die size over 500mm2 increasing with CAGR over 30% from 2019 to 2023 (number of products, not $).

Next, YP switched to new fab construction:

• 2017-2019 it averaged about 2 fab phases per year (based on construction start year). 
• 2020 6 phases
• 2021 7 phases
• 2022 3 phase
• 2023 2 phases
• Nanjin in production, going to 100,000 WPM
• Kumamoto (Japan) under construction (I don't think this is included in the above phase counts)
• Two fabs in Arizona under construction (not included either)

Those were all semiconductor fabs. There are also fabs for 3DFabric (advanced packaging). For advanced packaging, clean room space doubled from 2021 to 2025 (SoIC, InFO/CoWoS). SoIC will be about 30% of the total by 2025.

Press Lunch

During the press lunch, Kevin Zhang presented a few of the slides that had been presented earlier in the morning.

A few notes that I made:

RF is the largest specialty technology (now N6RF+). For future wireless communication (5G, 6G, WiFi7)

Old model: advanced nodes become mature nodes. That worked well until now, but now there is too much demand. So, having said last year that we would not do this, we have changed our minds and are expanding capacity in mature nodes (including Kumamoto).

Handel Jones asked about 1.4nm coming in 2027/28. Kevin said that it was early, and TSMC has an innovative approach, but he would not give any details (although he used the name A14 so I guess that is how nodes are going to be named after N2).

He also said that TSMC is very mindful of cost per transistor, even though that is not the gating factor for overall system optimization. 

Summary

A one-sentence summary of the symposium has to be:

Despite short-term volatility, the semiconductor market is growing exponentially long term, and TSMC is ready.

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