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TSMC had their annual Technology Symposium last week. As always, my post comes with a caveat: TSMC will not allow pictures to be taken, recordings to be made, and they don't hand out any materials. This is entirely fro my notes. That said, here's what we learned.
The day opened with a welcome from Rick Cassidy, President of TSMC North America. He reminded us that this was the 23rd time that TSMC had run this event. The US is clearly TSMC's largest market. Last year they built 5238 products, which consumed 5.8M 12" wafers. That represented 71% of TSMC's revenue, so not far off $3 out of every $4.
Mark Liu gave a high-level view of a lot of what would be revealed in more detail later in the day. He is TSMC's President and Co-CEO (C.C. Wei is the other). He said that TSMC's goal is to be their customers' "trusted technology and capacity provider" and emphasized that they do not compete with their customers.
He then re-iterated TSMC's focus on 4 market segments, and started to give some information about new capabilities for those segments:
YJ Mii talked about TSMC's technology leadership.
N5 (5nm) development is going at full speed, with risk production in 2019, volume production in 2020. It will use EUV for critical layers. Using EUV, the mask count for N5 will actually be slightly lower than N7 (that uses quadruple patterning in places, requiring at least 4 masks where EUV needs only a single mask).
Beyond FinFET, TSMC is planning horizontal nanowire, what they call gAA for gate-all-around. As the name implies, the source/channel/drain is built out of a number of wires running through the center of the gate giving even better control than FinFET. This is planned for 3nm. It has superior electrostatics for enhanced energy efficiency. Beyond FinFET they are also looking at germanium with Ge hGAA pFET that they have built having record performance (the picture showed a transistor using 4 nanowires).
They have also been working on tunnel FETs (TFETs) and have demonstrated III-V compound TFET basic building blocks.
In the interconnect area, they have a novel capping process that reduces interconnect resistivity. He didn't say much abut this but I assume it is to do with reducing via resistance. With a self-aligned via process, they feel they can scale interconnect down to 3nm.
Their EUV experience is that they currently have 125W source (they want 250W). They have a throughput of 1400 wafers/day/machine continuously. With novel EUV resists for 5nm they can replace 5 193i (normal lithography) with one and can get down to 26nm pitch.
40nm eMRAM risk production is 2H17 and 28nm in 2H 2018. TSMC feels that they have leadership in CMOS image sensor (CIS).
In packaging, they continue to innovate on both their solutions. The new InFO_on substrate (InFO-oS) has a large substrate for multi-die. They continue to push CoWoS for the larger modules, now up to 1500mm2 (around 1.75X the reticle size) with packages up to 65mm for more functionality and the capability to put lots of high-bandwidth memory (HBM) in the package.
Next up was actually Cliff Hou, but since his stuff fits in better with the detailed presentation in the afternoon, I'll leave his presentation until tomorrow's post. JK Wang gave an update on manufacturing.
There are 4 fabs under development. Fab 15 phase P5, P6 and P7 and the Nanjing fab (Nanjing is in China, not Taiwan). P5 and P6 are for the 10nm ramp. P7 will start construction in Q3 for expansion of N7 capacity. Nanjing has 2 phases planned with 40K wpm each. Equipment move-in for the first phase is Q4 2017 with production in Q4 2018.
Capacity from 2016 to 2017 will increase by 10% to a total of 11M 12" wafers. The primary increase is for 10nm, which isn't surprising. N10/N7 capacity will be 400K wafer in 2017, 800K in 2018 and 1.2M in 2019. More surprising is that 28nm is seeing very strong demand with a 15% year-on-year increase.
They are introducing what they call precision manufacturing. At any moment, they have 20-60 technologies, 50-150 customer and 500-1500 products. The data volume produced by the equipment increases exponentially with the node, by a factor of 75 between N10/N7 compared to N40. They have put in place a big data and machine learning infrastructure, and their domain knowledge plus neural networks gives them an "intelligent manufacturing environment."
The result: 99.5% on-time delivery.