Breakfast Bytes Blogs

This is the second of two posts about last week's TSMC Technology Symposium. The first was yesterday and covered the big picture presented in the morning.

It's a good job TSMC doesn't do countdowns for rocket launches. It seems to go 28...20, no wait, not 20...22...16...16 again...10, no, wait, not 10...12...7...7+...5...3.  But seeing how they bring a fab up into volume production, a rocket launch is a good description of the graph!

Cliff Hou

Actually, Cliff Hou, TSMC's VP of Research & Development and Technology Platform, presented in the morning but since his presentation serves in some ways as an introduction to more detailed presentations in the afternoon, I cover it today.

He kicked off by talking about N7 and N7+ readiness. N7 is ready for tapeouts and all tools will be certified by the end of March. Foundation IP (standard cells, memories etc) are ready. Some ecosystem IP (which is TSMC-speak for IP created by other companies such as Cadence) is validated in silicon. N7 (compared to 16FFC) gets either a 33% speed boost or a 58% power reduction (on an ARM core).

N7+, which uses several EUV layers to simplify the process and improve the routing, will get a further 10% performance boost, and the logic will be shrunk a further 15-20%. All design rules remain the same except for the EUV layers, which it seems are more aggressive. So to move from N7 to N7+ will require reimplementation to take advantage of the improved cell libraries, whereas SRAM, analog and I/O will just require re-characterization. 

Next, he talked about N12. 12FFC is an optical shrink from 16FFC, but some of the logic density and power reduction comes from the low-track standard-cell libraries, so it is best not to just shrink at the die level. Instead, logic should be re-implemented with the new libraries, but SRAM, analog, and I/O just require recharacterization. Comparing N12 to N16 there is a 20% area reduction with the 6-track library, or a 14% area reduction with the 6-track turbo library. There is also a higher performance 9-track library that obviously gives up more area. For HPC, there is a variant process with overdrive and larger contacted-poly-pitch (CPP). In the interconnect, there is wider metal, large vias and via pillars, where you can put vias on top of each other, and so get from low metal to high low-resistance metal without requiring much area and not requiring the risk of EM issues on intermediate layers. TSMC will be ready next month for N7 HPC. At N7+ HPC should get about another 4% improvement in performance or 15% in power versus N7.

TSMC has started to use machine learning to drive design tools, in particular, to produce optimization scripts for place & route of ARM processors. They will implement this in N7 for A72 in Q3 2017, and for A73 in Q4 2017. This includes routing detour prediction, clock gating latency and annotation, congestion prediction and static IR prediction.

BJ Woo

BJ Woo drew the short straw and had the first presentation after lunch. She didn't have to cope with everyone falling asleep having eaten too much, with just one hour to get an enormous hangar of a conference room fed, some people were still eating as she started. She talked about advanced technologies, in particular, the N10 ramp, achievements in N7 and N16, and two new processes at 12nm and 22nm.

She started by looking at CAGR growth rates from 2016-202 of the four priority areas for TSMC: smartphones at 7%, HPC at 10%, automotive at 12% and IoT at 25%. Then she came down to earth and tied these to specific TSMC processes and the expected migration paths:

• 20SoC, 16FF+, N10, N7, N7+ for high-end smartphone, HPC, automotive, games
• 28HPC, 28HPC+,16FFC, 12FFC, 7FFC for mainstream smartphone and automotive
• 50ULP,28HPC+, 28ULP, 22ULP, 12FFC/ULP for low power applications and IoT

Then she dug into more detail still, starting with N10/N7/N7+.

• N10 is in volume production with all technical and customer product qualification complete and volume production in F12 and F15
• N7 is targeted at mobile, HPC and automotive and will be "TSMC's finest technology, serving all segments." For power sensitive applications it will be even better than 16FFC but there as the optimized performance version for applications that demand the most performance, and it also fulfills automotive needs. Risk production is April 2017. More than 20 tapeouts are planned this year.
• N7+ will be ready in 2Q 2018.

The mainstream product offerings are 16FFC and 12FFC.

• There has been excellent 16nm yield learning, much steeper than was achieved at 28nm and 20nm (remember 20nm?). Cycle time is now less than 1 day/layer (also better than 20nm and 28nm).
• 16FFC has been certified for grade 1 automotive at 150°C. All 3rd party IP will be required to be ISO 26262 certified. Foundation IP is qualified with AEC-Q100
• This year is the launch of 12FFC with 1.1X speed or 0.7X power featuring 6-track standard cells, dual pitch BEOL, device boost, 6 track turbo standard cells, 10% speed gain or 25% power reduction and 10% area reduction compared to 16FFC.
• 12FFC is an optical shrink of 16FFC which means the design rules are the same (only scaled of course), the same layers, same SRAM cell layout, same voltage range, same I/O devices. It is best (but not required) to reimplement standard cell areas with the 6-track library, but everything else just requires characterization.
• 12FFC will be a "long-lived node". You might wonder what the short-lived nodes are and although BJ didn't say so explicitly they are 20nm (pretty much already gone) and 10nm (in production but clearly 16FFC to 12FFC to N7 is the path for anyone who is not an ultra-high-volume mobile customer).

For IoT and wearables, they have their own new process too, 22ULP (ULP stands for ultra-low-power).

• The migration path is 28HPC+ to 22ULP, also a direct optical shrink despite the very different process names. Transistors operate down to 0.6V
• Compared to 28HPC+, 22ULP gets 15% speed increase of a 35% power saving, along with a 10% area reduction

In summary, TSMC is moving fast:

• Accelerate the pace of new tech rollout for mobile and HPC
• Continue to invest in more cost-effective technology for mainstream products
• Offer leading ULP technologies for IoT
• World-class technology quality for automotive
• Offer leading edge RF technologies to meet emerging demand for 5G and beam-forming

Suk Lee

Suk Lee, another ex-Cadence name, talked about the EDA and IP portfolio, what TSMC calls OIP. He presented lots of what I think of traffic light charts, with colored dots showing which tools and IP are ready,  but since there were no handouts and it is impossible to write down about 50 colored dots in the 30 seconds the slide is up, I can't actually give the details.

But he did give more color in some specific areas.

For 12FFC, a lot of work needed to be done by physical design tools (Innovus) to improve pin access techniques to make the 6-track library usable. As Suk said, when he started in this industry, pin-access was a problem and it is still an issue today. The dual pitch BEOL means that existing 16FFC IP blocks can be dropped straight onto the chip, and the routers will handle the different pin access requirements that result. There is already a comprehensive 12FFC IP portfolio available since it is an optical shrink of 16FFC and so migration is fairly straightforward. There are also extension added to Verilog netlist for NFIN (number of FinFET fins) and power-down support.

For 7nm, there is area reduction though cut-metal handling (this means that metal is manufactured by laying down a full grid and then using a separate cut-mask to split it up, rather than laying down separate metal runs). This requires routers to be cut-aware. There are also additional multi-patterning process requirements that affects both routers and custom design. To get automotive reliability where it needs to be requires statistical EM analysis and low Vdd enablement requires statistical-on-chip-variation down to 0.6V.

More about the 7nm design infrastructure:

• Area reduction through cut-metal handling (cut in routing, not just in the std cells). Routers are cut metal aware
• Compliance with multi-patterning process requirements
• Superior reliability with statistical EM reliability analysis (automotive)
• Low Vdd enablement with SOCV (statistical on-chip variation) down to 0.6V

Suk wrapped up with a summary of OIP:

• There are 14,000 IP titles, some of which are standard cell libraries that themselves contain thousands of cells
• All major IP types
• There are over 8,200 technology files for EDA tools in the various processes
• 97 partners participate in OIP, it dropped a little in 2016 due to consolidation but some new entrants mean the number has risen again