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Yujun Li, TSMC's director of business development for high-performance computing (HPC) which also includes mobile, presented Advanced Technology for Smartphone and HPC Platforms. Since that includes the most advanced nodes of N3 (3nm), this is probably the area most important as a driver for EDA and advanced IP. I will cover what she said.
She started with a look at the drivers for the semiconductor industry, where now over half of IT spending goes on cloud data centers. The semiconductor industry is expected to get to $500B by the end of this year. All the numbers are big, but I'm sure you've seen plenty of presentations on smart cities, and 5G, and AI enablement. So let's go to the small numbers. Here is TSMC's advanced-node process roadmap, with the years on the chart corresponding to the introduction of volume productions.
The roadmap is divided into two, with the highest performance at the top, and what TSMC is now calling mainstream at the bottom, with the process and libraries more optimized for power and area.
The new kid on the block is N3, scheduled for volume production next year. As you can see from the above table, N3 compared to N5 is 10-15% faster or 25-30% lower power. Logic density is up by about 1.7X, SRAM by 1.2X, and analog ekes out a small improvement.
There are actually three different N3 libraries. As you can see the N3 HPC library gets the advertised 15% improvement over N5. Or the N3 HD library shrinks the design to nearly half the area, at the same performance. And there is an HC library that gives both an increase in performance and an increase in density.
The most advanced process currently in volume manufacturing is N5. One of the most amazing things is the volume ramp from a standing start. The N5 ramp is even faster than N7 was, and lot faster than N16. There is also a big ramp in tapeouts with over 40 new N5 tapeouts expected this year, let by HPC and 5G infrastructure.
Next, Yujun moved on to N4, which was introduced last year. This is an optical shrink of N5 and so has the same design rules. The shrink delivers a 6% smaller die area, and there is also a simplification of the process with a reduced number of masks. better power and performance (than N5) with the same yield. Risk production of N4 starts in Q3 of this year.
One of the big challenges at all these advanced nodes is EUV mask defect and lifetime. As you probably know, these are actually mirrors and the entire system is enclosed in a deep vacuum. Defects are down to a third of what they were in 2018, and mask lifetime is up 4X, almost the same as with conventional lithography.
Finally, there are two new processes: N7HPC and N5HPC with overdrive. These have higher performance at the cost of some increase in leakage. This is the first time since 28nm that TSMC has had a process optimized for HPC. Data is in the tables below:
The summary of what will be available when:
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