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Paul McLellan

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Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC

• 3 minute read

breakfast bytes logoLast week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says:

Cadence Design Systems, Inc today announced that the Cadence LPDDR4/4X memory IP subsystem, utilizing the TSMC 16nm FinFET Compact (16FFC) automotive process technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for ADAS and L3/L4 autonomous driving applications.

That's a lot of jargon in a few lines. Let me unpack it.

  • I'm just going to assume you know who Cadence and TSMC are.
  • LPDDR4 is a memory interface standard, consisting of a PHY (an analog component that communicates with the actual memory chips) and a memory controller.
  • 16FFC is the second generation of TSMC's 16nm FinFET process. The automotive version of the process has an extended temperature range, more reliability data, and additional tracking of devices through the manufacturing flow.
  • ISO 26262 is the international automotive functional safety standard. The second edition was released at the end of last year (which includes a new chapter 11 focused on semiconductors).
  • ASIL is "automotive safety integrity level" and C is the third level (the levels run from A to D, although A is a sort of non-existent level meaning no safety requirement).
  • SGS-TÜV Saar is a company based in Sulzbach Germany (near the French border) that performs certification testing.
  • ADAS is "advanced driver assistance system" and L3/4 are two of the levels of automation of "driverless cars" (see the table below from the Society of Automotive Engineers). Today, many cars are level 2 (Tesla being the most visible), and a couple (Audi, Cadillac) claim level 3. Level 5 is true autonomous driving where no steering wheel is even required, which is probably at least a decade away if not more.

As is so often the case, I've covered almost everything that you need to know already. You should be reading Breakfast Bytes every morning!

The key takeaway is that the Cadence LPDDR4 IP can be used in safety-critical chip designs for automotive applications. The automotive semiconductor market is very different from many other markets such as mobile, primarily because of safety and reliability requirements:

  • Cars last 15-20 years, mobile phones just a few.
  • If your phone SoC crashes, you restart it. This is annoying. If your car SoC crashes, your car might literally crash. This is life threatening.
  • Phones have to work over the temperature range of your pocket. Cars have to work in northern Canada in winter, and the Arizona desert in summer.

The big challenge is that cars have to be safer than semiconductors are capable of delivering directly. As I put it in my post CDNLive EMEA: Do You Know What a FIT Is?

Functional safety is measured in FITS, which stands for "failures in time" and is the number of failures per billion hours of operation. The requirement for the whole car is perhaps FITS < 10, so less than ten failures of a vehicle in a billion hours of operation. This is then hierarchically partitioned out to the various subsystems, 1 FIT here, 1 FIT there. By the time you get down to an individual SoC, the requirement may be a FIT < 0.1. The challenge is that 28nm has a FIT of around 500 without any additional error handling, such as error correcting codes or redundancy. And 16nm is even worse.

 

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