Who was Taiwan's first semiconductor company? Who was Taiwan's first foundry? If you said UMC, you are right,  but you probably didn't. UMC stands for United Microelectronics Corporation (although people rarely spell it out, they just use the initials). It was created 40 years ago in 1980 as a spinoff from ITRI (the Taiwanese government's research institute). At the time it was not a pure-play foundry, it produced microcontrollers, chipsets, and other products before becoming a foundry service provider in 1995.

UMC has four 300mm fabs, along with several older 200mm fabs.

• Fab 12A in Tainan (Taiwan), with a capacity of 83,000 300mm wafers per month, 0.13um to 14nm.
• Fab 12i in Singapore, with a capacity of 50,000 wafers per month, 0.13um to 40nm.
• Xiamen, China, with a capacity of 50,000 wafers per month (when fully equipped), 65nm to 28nm.
• Kuwana, Mie (Japan) with a capacity of 33,000 wafers per month, 90nm to 40nm (acquired just a few months ago).

Here is a complete list of UMC's fabs, along with which process nodes they run.

The first time I went to Taiwan, I visited UMC. I'm guessing that was in Compass days, although I don't exactly remember the year. I was surprised to find that its headquarters was across the street from its primary competitor. Literally across the street. Buildings seem to have moved around now. In fact, Hsinchu in general looks totally different from how it did 25 years ago.

I tried to find some old pictures from much earlier. It turns out that Hsinchu is over 400 years old, one of the oldest cities in northern Taiwan (despite the Hsin in Hsinchu meaning "new", just like the Pont Neuf is the oldest bridge over the river in Paris). Of course, that pre-dates photography, but I still couldn't find any dramatic pictures showing a tiny village that is now a huge semiconductor complex. You'll have to make do with a picture of "Old Street", although judging by the cars this is a pretty recent picture:

Test Chip

At the end of last year, Cadence announced DDR 4/3, LPDDR 4/3,and PCI Express (PCIe) 3.1 on UMC's 28HPC+ process. This wasn't just taping out some design IP, a test chip was built and everything has been tested in silicon. These IP products are targeted at mobile computing, IoT, consumer, and other power-sensitive applications.

For Design IP products a decade ago, it used to be a "make versus buy" decision: is it cheaper to pay our own people to design it or is it cheaper to go and buy something from an IP supplier? However, that equation has changed a lot. Most design groups are simply not capable of designing these technologies, and from a strategic point of view, it makes little sense to put a major investment into a "me too" product. Standards-based IP like this is almost "me too" by definition since the main requirement is that it meets the standard. Of course, there are some secondary attributes such as area and power, but it is most unlikely that a semiconductor company is going to be able to improve on the teams of specialists that a company like Cadence has in its design IP engineering teams, who do nothing else but this kind of design every day.

Back in the 1990s when I was at Compass, we had the same argument, even though IP was mostly standard cells and memories, what we now call foundation IP. Our designers did nothing else but design those types of libraries. At our potential customers, if they decided to design their own standard cell libraries, it was likely to be a team of entry-level engineers who had never done it before. And they would never do it again either, since they would want to move onto the more important system-level blocks that provided their employers' differentiation.

There is another reason to license IP, too. Complex technologies like this require testing in silicon. If you license IP from Cadence, you get a design that has already seen silicon and been tested. If you do your own design, apart from the difficulty, you are putting a test chip on the critical path to tapeout of your real SoC.

UMC's Strategy

You might be surprised that this tapeout is in 28nm, not the most leading-edge node. The big reason for that is that, in 2017, UMC decided to move away from the race to the end of Moore's Law. In an interview with DigiTimes, UMC co-presidents Jason Wang and SC Chien said:

UMC encountered some bottlenecks in the 0.13-micron process race. It was a vicious circle in which we lost market share in the advanced-node market segment and saw impacts on our revenues, coupled with a decline in our available R&D capital. Such experience pushed UMC to rethink its strategy to avoid being trapped again in a rat race. In 2017, UMC recognized its role could make a difference. Rather than fighting to be a technology leader in the advanced-node process segment, UMC can be more capable of being a leader in the more mature process segments.
...
There were a number of factors we had considered behind the decision we made in 2017. As UMC steps into the FinFET segment, we intend to put our capex focus on technology R&D rather than manufacturing capacity. In fact, UMC's investment in 28nm manufacturing capacity has still been a burden for the company. As we enter the era of FinFET, we want to slow down the pace of expansion and pursue our growth in mature and specialty market segments for profitability.

When asked about the Japanese fab that they acquired last year, Wang pointed out what a great deal it was:

We have just fully acquired Japan's Mie Fujitsu Semiconductor (MIFS), renamed United Semiconductor Japan (USJC) on October 1, 2019, for US$600 million, bringing us a monthly foundry capacity of over 30,000 12-inch wafers. It's good investment, given that the capacity, if built on our own, would involve a construction cost more than five times the acquisition cost.

More Details

More details on Cadence's IP can be found on the respective product pages:

• DDR and LPDDR
• PCIe

Although nothing directly to do with the testchip, although I'm sure it was used during the design, there is also Verification IP (VIP) available for all these interfaces.

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