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Some things in semiconductor manufacturing sound made up when you first hear about them. Through silicon vias? You're joking, right? Chemical-mechanical polishing/planarization (CMP)? You mean after all that super thousand-times-cleaner-than-an-operating-theater stuff, you just slap the wafer down on a grinder? But, of course, both of these are true. You can't put 12 layers of metal on a wafer by just alternating layers of interconnect and contacts without doing something to make sure that you keep a planar surface on the top of the wafer. Otherwise, various unevenness can result, such as dishing.
CMP is one part of that puzzle, but on its own, it isn't good enough. On any layers where there are big gaps without any interconnect, there is a large low area that remains low even after the CMP step. Large areas like this are not unusual—for example, the area above large memories or analog blocks is often kept clear of signals resulting in large areas where no metal occurs naturally.
So, along with CMP, another part of the puzzle is not to have any large gaps without interconnect, and this is done by automatically adding metal into those gaps. This is known as dummy metal fill, or just metal fill. If it is on a layer other than metal it is usually just called dummy fill.
This used to be added very late in the design cycle after all the signoff timing had been completed. The additional capacitance that resulted from the dummy metal was simply ignored, even though it would make the design marginally slower. It turns out that back at 40nm, the effect on timing was 0.12%. This is probably less than the mismatch between static timing and SPICE, and ignoring it was perfectly reasonable. However, by 16nm, the error was more like 4%. At 10nm, 7nm, and beyond, it will only get worse, above 5%. This is not something that can be ignored any more.
But not ignoring dummy metal brings its own issues. First, the whole die needs to be analyzed and all the additional polygons added. Then they need to go through extraction to get the correct parasitics, and these need to be taken account of during timing verification and physical verification. Of course, for final signoff, where you want the greatest accuracy possible, you need to do this. But earlier in the design cycle, it is ideal to have something that captures the effect of dummy metal fill without increasing the time required to go around the ECO/timing loops during the drive towards signoff.
This is where Integrated Virtual Metal Fill (IVMF) comes in. Instead of building all the polygons and then analyzing them, the effect of doing this is modeled straight from the rules on how the metal should be added, going straight to estimates of the parasitics that result, which can then be fed into static timing verification in the normal way.
The above charts compare IVMF with the real metal fill, with very close correlation. To be useful, IVMF is not just a point solution. It needs to be tightly integrated into place and route and to extraction. Other tools, such as static timing, should work normally, since to them it is just parasitic capacitance.
The designer can control how metal fill is inserted, typically so that it is similar to the routing on the layer, with the same primary direction, spacing. The overall metal density is set by the manufacturing process and normally will be checked as part of final physical verification. Metal fill is especially important for long nets in the most advanced processes, since without estimating the effect of metal fill the timing can be off on these large nets by as much as 17% (at 7nm). Adding IVMF reduces that to below 1% even on these most extreme nets.
The charts above show the effect of IVMF capacitance accuracy on the large nets of a 7nm design. Metal fill can contribute as much as 17% on large nets, with a big impact on timing (on the left). Quantus IVMF shows tight correlation with the actual numbers on these larger nets, greater than 50fF capacitance (on the right). It also has better average (0%) and standard deviations (1.55%) on all the nets. Smaller nets have less impact on timing but the errors can be large, with capacitance variation of as much as 40%, but Quantus IVMF brings that down to 2%.
Another question I've often heard is, "What is the metal fill connected to?" The answer is nothing, it is left floating. There are various debates about whether it makes sense to put vias underneath it when possible, but that seems mostly to increase the capacitance to the substrate by effectively moving the plate closer to the substrate. Of course, in a real circuit, floating nodes are a problem because a gate that is between Vss and Vdd will leave both the p-transistor and the n-transistor of a CMOS gate partially on, resulting in crowbar current and high power consumption. However, the metal fill polygons are not connected to gates so this isn't a problem.
See a video by Hao Ji, the R&D manager of the Quantus product.
For more information, see the Quantus QRC Extraction Solution page.
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