Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and multiple patterning—which have changed a lot of the rules for custom design (which doesn't just mean analog, but also standard-cell design and other digital IP). The digital designer is largely insulated from these. He or she never looks inside the standard cells and so never sees a transistor. It matters little to them if the transistor is planar or FinFET. The double patterning is largely taken care of by the router, which has to be aware of the coloring for routes, often for contacts/vias, and perhaps for cut masks and other artifacts that don't really even appear explicitly in the layout.

Double patterning is often referred to in terms of colors (red and green for double patterning) and the process of assigning a piece of layout (whether automatically or manually) to a mask is called coloring. This actually comes from mathematics since this type of problem is known as graph-coloring and so automatically assigning polygons to nets is a coloring problem (as are many other processes such as register assignment in a software compiler).

For the custom designer, these two changes make a huge difference:

• Transistor width and length cannot be varied—the choice is how many transistors and only a whole number of transistors is allowed
• Since FinFETs have the gate wrapped around the fin, and have high drive current, electrical and thermal effects can't just be left until signoff any more
• The design rules are extremely complex with dummy structures and a highly constrained layout style, layout dependent effects, voltage dependent design rules, and more
• For critical nets, such as differential pairs, manual coloring is allowed, but the foundries only allow a certain percentage (around 20%) of nets to be manually colored since badly colored designs can impact yield

Cadence released Virtuoso Advanced Node in 2013 to provide full support for designs in the 14-22nm range. The new release announced today provides full support for 10nm with some support for 7nm features, too. Cadence has been working with advanced customers and foundries on 10nm for some time, so the new features have already been matured on some of the most demanding designs. All the first shuttle customers at 10nm use Virtuoso.

At 10nm, there are a lot more changes. Everything gets more complex. There is a structured row-based methodology that is needed so place and route can work. EM constraints can be severe with skinny wires being driven with high current. The design rules are even more impossible for a layout designer to completely comprehend, with an increase in layout dependent effects (LDE) and density gradient effects (DGE).

So what are the new features? Jeremiah Cessna went over it with me in an information dump last week. Drinking and firehoses come to mind. These new features are not necessarily limited to 10nm, when appropriate they are available in 14/16nm (and probably earlier processes if you insist).

Multi-Patterning and Color-Aware Layout

The first big change is that at 10nm is that the foundries require the design to be fully colored before it is taped out. This can require next-generation double patterning, not just LELE (litho-etch-litho-etch), but also SADP (self-aligned double-patterning), via cut double patterning, triple, quadruple, and even quintuple patterning. Support includes ways to propagate coloring (so every polygon does not need to be colored), a correct-by-construction SADP flow, ability to lock colors and so on. Designs can be precolored in the schematic to make sure that critical nets, such as differential pairs, can be assigned to the same mask.

An alternative approach that can be used is to create a color grid. This approach is especially important when there are wide wires since the spacing of wires depends on the width and so a common pattern is to group all the wide wires in the middle, with the narrow wires outside. The color grid reflects this, so it is not an even grid. Objects inherit the colors of tracks used to create and edit the wires.

Module Generator Device Array Flow

The traditional custom flow, still used for older nodes, is that the designer would create the schematic and use simulation to adjust it until it seemed good. It would then be shipped over the wall (or the ocean) to the layout designer. Once the layout was done, which might take a week, the parasitics would be extracted and then the design could be resimulated and the process could iterate if required until it converged. This method got less effective with every node, but by 10nm, drawing a transistor netlist and simulating it without layout is a waste of time since it is too inaccurate to give any useful feedback. That raises the issue of what the flow should be since it is very expensive to do layout just to find out when it is simulated that the wrong approach was taken and a new schematic and a new layout are required.

Over the years there have been many attempts to automate custom layout (Jeremiah Cessna was at NeoLinear for example, acquired by Cadence in 2004) and all failed to truly impact the methodology. The reason was that there is too much flexibility, and inputting enough constraints to deal with that was more work that doing the layout manually. So suddenly the highly restricted design style that FinFETs and lithography imposes make higher levels of automation possible. Using ModGens, it is possible to create large multi-transistor structures complete with well-estimated parasitics.

A good analogy is that these are super-Pcells that generate higher level objects such as differential pairs, cascodes, stacks of series devices, HiR resistors with current mirrors, varactors, decap, and more to come. Of course customers can build their own generators too.

Using ModGen-based flows (as opposed to the old schematic-layout loop) greatly reduces the number of design iterations and can improve designer productivity by up to 25X.

Electrically Aware Design

The electrical rules are increasingly complex and it is also increasingly easy to violate them. With electrically aware design (EAD), the rules are checked in real time as the layout is being done. For example, if a line gets too long and violates an EM current rule then it switches to red. If R & C matching is specified, then this is checked in real time. Normally, ERC checks require a design to be LVS clean, but during layout this obviously cannot be guaranteed. The electrically aware rule checking works on non-LVS-clean designs.

10nm Custom Routing

For 10nm, custom routing supports the new design rules, and minimizes coloring errors that can otherwise be widespread at 10nm.

In-Design Physical Verification

In-design physical verification (iPVS) basically does what it says on the can. It enables layout engineers to instantaneously detect and fix errors as designs are being implemented as opposed to waiting for a large amount of design to be done before running a DRC check. This feature alone seems to improve designer productivity by 15%.