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Paul McLellan
30 Oct 2019

Implementing Automotive Radar on Tensilica Processors


breakfast bytes logonvidia radarThe big controversy about sensors in autonomous driving is whether lidar is essential. Radar has improved significantly in resolution and so I like to phrase the question as to whether radar is getting better faster than lidar is getting cheaper. Today's focus is on radar since the technology is playing an increasingly important role, driven by automotive ADAS applications. These applications require higher performance and more capabilities from the radar module to determine distance, direction, and speed of targets in a multi-target scenario.

The radar technology used is known as frequency modulated continuous wave (FMCW), typically in the 77GHz band. Instead of putting out individual radar pulses and measuring the time-of-flight for the echo to return, the radar is transmitted continuously but with frequency varying, typically in a linear sawtooth wave.

frequency modulated chirp

The chirps illuminate the objects around the vehicle and depending on their distance and speed, the returning signals (from multiple chirps) can be analyzed to determine the distance and size of the objects, how fast they are moving, and what direction.There may be just a single transmitter antenna, or digital beamforming can be used there to steer the radar beam. Of course, the critical function is that all the targets of interest are illuminated. This all requires a lot of signal processing for receiver digital beamforming (DBF) to start with. If you know what steerable beams are in 5G, then this is the opposite. Instead of doing phase array transmission on lots of antennas, it is doing the same thing in reverse, using multiple antennas to work out where signals came from. Then there is the 2D range-Doppler FFT processing with windowing and 2D constant false alarm rate (CFAR) kernels.

A typical automotive application will have multiple receiver antennas. A simplified block diagram of a radar unit appears below.

In linear sawtooth FMCW, the transmitted waveform is a sequence of linear chirp signals, and the reflected received signals are mixed with the transmitted signals to generate the beat signal. The beat signal is the baseband signal, which is sampled by the ADCs and sent to the DSP. The total duration of the multiple chirp sequence transmission is called the coherent processing interval (CPI). For one CPI, the ADCs generate a data sequence that is sampled along three dimensions: range dimension (time sampling of one chirp), Doppler dimension (multiple chirps), and channel dimension (each antenna element). This three-dimensional data sequence for one CPI is the received radar data cube, which is processed by the signal processing algorithm chain on the DSP. The sizes of the various dimensions are chosen based on required range, speed, and direction resolutions. The chirp rate might be as little as 10us, whereas the CPI used for analysis might be 25ms. An example of the datacube is shown below.

Because radar modules typically operate in multiple modes—for example, a “search mode” to scan for objects and “track mode” to track specific objects of interest—adaptability and multi-function operation are essential. This means a specialized DSP with an appropriate instruction set is required. Cadence has two members of the Tensilica family that are designed for this application The Tensilica Fusion G3 DSP is most suitable for fixed-point radar implementations. The ConnX BBE32EP is most suitable for high-performance floating-point implementations.

Tensilica Fusion G3 DSP—A very long instruction word (VLIW) vector SIMD architecture targeting multi-purpose applications with an optional floating-point unit. The Fusion G3 DSP supports floating-point and fixed-point DSP operations with a comprehensive range of data types, in addition to the scalar Xtensa real-time controller, making it ideal for a wide mix of compute-intensive signal processing and control applications. This DSP supports operations on 8-, 16-, 32-, and 64-bit signed and unsigned integer types, and single- and double-precision floating-point types. It supports multi-way vectorization, depending upon the data type (integer/float/double-precision), as well as 2/4/8/16-way multiplier-accumulators (MACs) with 20/40/80-bit accumulation precision.

Tensilica ConnX BBE32EP—A 16-way VLIW SIMD DSP, supporting 16-bit and 32-bit fixed-point complex vector operations. The ConnX BBE32EP is an ultra-high-performance DSP architecture designed for next-generation complex signal processing applications. It combines 16-way single instruction, multiple data (SIMD), 32 16x16-bit MACs, and up to a 5-issue VLIW architecture with a set of versatile pipelined execution units. These units support flexible-precision real and complex multiply-add, bit manipulation, data shift and normalization, data select, shuffle, and interleave operations.

Learn More

Earlier this year, I wrote about the most recent member of the ConnX family in Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar.

For a much more technical deep dive, read the white paper Fixed- and Floating-Point FMCW Radar Signal Processing with Tensilica DSPs. This paper contains much more detail of the implementation of an example automotive radar system using the two processors above.

 

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