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I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes, basically anything at 5nm and below, use EUV lithography (extreme ultraviolet). You probably also know that only one company in the world, ASML in the Netherlands, manufactures the scanners. The current generation has a numerical aperture of 0.33 and so is known as 0.33 NA. The numerical aperture is a measure of how much light the optical system can collect and focus. It's not a perfect analogy, but it is a bit like the F-stop on a camera. The problem with 0.33 NA going forward is that it will require double patterning even with 13.5nm light. This means that the overlay accuracy needs to be very good (since two masks are needed for double patterned layers), and obviously the manufacturing cycle-time is slower with the extra steps, and yields will be lower since extra steps are extra opportunities for defects to get introduced. In the keynote at the recent SPIE Advanced Lithography Conference, Intel said that it doesn't want to go to double patterned EUV, so high-NA is needed.
One thing that you can tell from the above picture is just how huge these machines are. On the left is 0.33 NA EUV used in volume manufacturing at all the leading-edge manufacturers. On the right is how big a high-NA EUV scanner is. Note the person for scale since you probably don't have much of a feel for how big a 0.33 NA machine is (I've seen the one at imec and it is already huge).
Obviously, ASML, along with its optical partner Zeiss, is hard at work on developing the scanner. Imec, in Leuven, just outside Brussels in Belgium, is working on the rest of the infrastructure, in particular:
Last week I talked to Kurt Ronse of imec to get an update. At the recent SPIE Advanced Lithography Conference, imec presented several papers on various aspects of high-NA EUV.
Imec and ASML have created a high-NA lab, which will receive the first scanner from ASML. The timeline to insert high-NA EUV is only 3 years from when the first prototype will be delivered next year. The lab is at Veldhoven, ASML's home, since it would probably take about 6 months to dismantle the machine in Veldhoven, where it will have been assembled, in order to move it to imec's cleanroom. This is a tight schedule—if you remember, it took over a decade to bring 0.33 NA EUV into volume production. There is a TEL track to link to the scanner being installed this year to handle the wafers. The scanner will be available in 2Q next year.
It turns out a lot of work for high-NA EUV can be done by squeezing the ultimate resolution out of the 0.33 NA EUV scanner that imec already has installed in its development fab. It is really slow, so not suitable for real production, but experimental work on photoresist and metrology has been going on for some time. All the resist suppliers are at imec testing new samples all the time. Wafers are being manufactured with 24nm pitch.
The high-NA scanner will bring better resolution and so no double patterning, but the depth of field will be much smaller. As a result, the resist will need to be thinned down and that brings two problems: increased line edge roughness (LER) and poorer metrology due to the limited image contrast with the thinner resist.
With thinner resist, it is hard to make a nice picture and measure line width and LER. So imec is working with the metrology suppliers to improve the tools and improve contrast. Of course, one of the things imec is doing is manufacturing wafers for the metrology suppliers to use for testing, both optical and e-beam. The plan is to use the best-known metrology methods once the high-NA scanner starts to produce wafers next year.
The masks (actually mirrors) for high-NA EUV are anamorphic, stretched 8X in one direction with the other remaining as 4X. The machine can also use the same 4X in both directions masks used in 0.33 NA. The original plan was to go 8X in both directions on a 9" blank, but the mask-making infrastructure could not cope with that. One issue with these "half field" masks is that the biggest designs will require two masks, and then stitching together. About 90% of designs are smaller than this and don't have this issue.
An issue for EUV masks is that the standard absorber is not the ideal choice for having the best contrast. So the industry is investigating alternative absorber materials. This requires the whole mask ecosystem to change. The material needs to be compatible with the scanner (which has a certain amount of hydrogen radicals in the vacuum which can attack some material). It also needs to be compatible with cleaners, the mask shop needs to be able to etch it and stop on the Ruthenium capping layer, and so on. The big advantage is that the contrast to the image in the scanner would get better. The conclusion from imec's experiments is that the best options for the future are TaCo and Ta2Co for a new absorber material.
The light source in the high-NA scanner is exactly the same as in the 0.33 NA scanner. It will gradually creep up as further optimization is done, and that will improve the 0.33 NA scanners too. Further, there is better transmission through the mirrors on the light path, so there is a slightly, perhaps 10%, slightly higher throughput.
I asked Kurt about pellicles. He told me that today memory companies don't use pellicles since they have enough redundancy in the architecture of the memories, and they want to keep their manufacturing as fast as possible. Since the pellicle absorbs some light, it slows the scanner down. Logic companies use pellicles since defects cannot really be tolerated in logic and still get a working chip.
Newer generations of pellicle materials can approach 90% transmission and withstand 250-300W of source power (beyond that, they heat up too much and become brittle). The current generation of pellicles uses polysilicon as the material. imec is experimenting on alternative pellicles using carbon nanotubes, which transmit 95% so throughput goes down less and it can withstand very high heat. It remains to prove that the lifetime of these pellicles is 10,000 wafers, which is the spec. Something like this will be required if the source power gets to 600W.
Another issue is that the current polysilicon pellicles from ASML don't transmit DUV, which is used for inspection. So for mask inspection the pellicle has to be removed, the mask inspected with DUV, and then the pellicle remounted. Carbon nanotube pellicles allow through pellicle inspection since they transmit DUV.
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