What’s for Breakfast? Preview October 3rd to 7th (video)

Monday: Options for 5nm. Silicon can only cut off sub-threshold at 60mV/decade. There are two ways to get more, the blue pill and the red pill.

Tuesday: Training bytes, 1200 videos to allow self-instruction on many aspects of Cadence tools. Most are under 5 minutes long.

Wednseday: The latest Tensilica LX7 processor, and using floating-point for DSP/

Thursday: Verific make SystemVerilog and VHDL parsers. All EDA companies make use of them.

Friday: Cadence and ARM worked together on a 10nm implementation, which they presented at the recent TSMC OIP Symposium.