How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution

Is the generation of SDC Constraints for DFT Constructs in Genus Synthesis Solution a topic you are not yet familiar with? If you are inserting Fullscan or any other advanced DFT logic like OPCG, Boundary Scan, PMBIST, Compression, LBIST, and IEEE 1500, worry no more about the DFT-related SDCs extraction. Cadence has you covered with the simple methodology to automatically generate SDC constraints for any DFT construct.

The solution that Genus offers requires only three main steps in order to generate DFT SDCs for three base timing modes: the shift mode that holds constraints for timing the DFT shift operation of one or more testmodes, the capture mode that holds constraints for timing the DFT capture operation of one or more testmodes, and of course, the non-DFT mode that is the mode holding the constraints for timing the design when the DFT logic is disabled.

All you simply need to do is import the functional SDCs if present, set the relevant root attribute that controls the generation of DFT SDCs to the correct value, and finally, export the generated DFT constraints for the different timing modes by using the relevant command.

If all this sounds interesting, use the following material and find out everything you need to know about the DFT SDC methodology in order to master the generation of SDC constraints for any DFT construct you wish to insert into your design.

 How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution?(Video) 

Refer to Generating SDC Constraints for DFT Constructs chapter of Genus Design for Test Guide

For more videos on other topics do refer to the whole video library at the support portal.

Note: Enroll in the corresponding training at the  Cadence Support for lab instructions and a downloadable design.

Genus Synthesis Solution with Stylus Common UI v21.1 (Online)

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