Unlocking AI-Driven Chip Optimization with Cadence Cerebrus

Join us for a technical deep-dive into the future of digital implementation with the Cadence Cerebrus Intelligent Chip Explorer. This webinar explores how generative AI is transforming chip design by automating flow optimization to achieve aggressive Power, Performance, and Area (PPA) targets.

Learn how to transition from labor-intensive manual tuning to an autonomous, AI-driven methodology that optimizes multiple blocks concurrently. By leveraging these advanced capabilities, engineering teams can significantly improve productivity and compress design closure cycles.

We will also introduce the Cadence Cerebrus AI Studio, the next evolution in the Cerebrus portfolio. Discover how its advanced Agentic AI features optimize entire subsystems and SoCs, drastically reducing overall Time-to-Market.

Technical Agenda: 

•      Product introduction: Maximizing design throughput using the latest AI-enhanced features.
•      Tool configuration: A strategic guide to practical implementation and deployment.
•      Methodology and scalability: Best practices for establishing high-performance Cerebrus environments.
•      Next-gen capabilities: A technical deep dive into Cerebrus AI Studio for subsystem-level optimization.

Date and Time

Wednesday, February 25

07:00 – 08:00 PST San Jose/10:00 – 11:00 EST New York/15:00 – 16:00 GMT London/16:00 – 17:00 CET Berlin/17:00 – 18:00 IST Jerusalem/20:30 – 21:30 IST Bengaluru (Bangalore)/23:00 – 00:00) CST Beijing

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Training Bytes

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Blogs

• Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer - Digital Design - Cadence Blogs - Cadence Community
• Placing Macros and Standard Cells Concurrently - Digital Design - Cadence Blogs - Cadence Community
• https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/acceleratedlearning_2d00_part-2
• Innovus Implementation System 25.1: A Big Leap Forward - Digital Design - Cadence Blogs - Cadence Community

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