Innovus Implementation System 25.1: A Big Leap Forward

The latest Innovus 25.1 major release, packed full of new features and improvements that are sure to enhance your design experience, is now available on the Cadence downloads portal. One of the most exciting additions is the Innovus Synthesis feature.

This RTL Synthesis capability, integrated into the Innovus Implementation System software, offers numerous benefits. It primarily focuses on improving design turnaround time (TAT) by providing a complete RTL-to-GDS flow in one tool and achieving superior power, performance, and area (PPA) results. Key advantages include faster workflows, scalability for large designs, comprehensive foundry support, and a unified user experience.

For more on how to run Innovus Synthesis, view the demo on the Cadence ASK portal:

We have also updated and released our Innovus training courses for 25.1:

• Innovus Block Implementation with Stylus Common UI: In this course, you learn how to use the Innovus Implementation System software using the Stylus Common User Interface (UI) to achieve the best power, performance, and area (PPA) for your design. You will learn techniques for synthesizing your RTL with the Innovus Synthesis Platform, floorplanning and placement using solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.
• Innovus Hierarchical Implementation with Stylus Common UI: In this course, you explore the features of the Innovus Implementation System software using the Stylus Common User Interface (UI) for creating and implementing a hierarchical design. You learn several techniques to floorplan your design, create partitions (hierarchical blocks), run place-and-route, and optimize the design (at the block level and top level) to close timing. You learn techniques to reduce memory size and run time using interface logic models (ILMs). You will also learn how to use blackboxes, FlexModels, and SoC architecture information technology to prototype a design when a complete netlist is not available and explore the benefits of using the Integrated Hierarchical Database (iHDB) flow to reduce memory, runtime, and TAT.

Our training classes are designed to help you master the latest features and enhancements. Whether you're a seasoned pro or new to the game, these courses have something for everyone.

There is also a Digital Badge available for the trainings. A digital badge from Cadence Training makes sure your skills get noticed! Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust.

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Choose the Cadence Training Menu that's right for you.

Happy Learning!