4th Tensilica Day(s!) in Hannover: Doubling the Days, Doubling the Fun

The popularity of the Tensilica day events in previous years (last year's presentations, blog), led to increasing this year’s event from one day to two days of technical presentations and demos.

As the tradition goes on, on 23rd and 24th of September, attendees from both academia and industry gathered at the “Königliche Pferdestall” (Royal Stables) conference centre in Leibniz University Hannover (LU Hannover—a new, beautifully renovated hall which hosted more than 110 attendees.

The event kicked off with a welcome message given by Prof. Holger Blume, Institute of Microelectronic Systems, LU Hannover. Next up, Richard Sproul, Product Solution Architect from the Cadence EMEA field team, presented a technical introduction to Tensilica products with highlights to the new Tensilica Vision Q7 DSP core.

The rest of the first day was dedicated to two topics: Neural Network Acceleration and Theory & Software Tooling.

Neural Network Acceleration:

Some of the highlights include two presentations from academia, the first one regarding Configurable Processing Elements for Flexible Acceleration of Variable Precision Neural Networks, presented by Technical University of Munich, and the second one regarding CNN Inference on Coarse-Grain Reconfigurable Arrays under Throughput Constraints, presented by Friedrich-Alexander-University Erlangen-Nürnberg. The last presentation of this session was given by Dresden University of Technology and introduced A Power Efficient Network Coding Accelerator: A case study based on the Xtensa® Processor with the Tensilica Instruction-Set Extension from Vodafone Chair, Mobile Communication Systems.

Theory & Software Tooling:

This topic discussion started with a talk regarding Exploration of Memory Energy-Reduction Strategies for a Deep Learning ASIP from RWTH Aachen University and concluded with Evaluation and Optimization of a Tensilica processor for hearing aids from LU Hannover – a 22nm FDX Ultra Low Power Design based on Cadence Tensilica Processor Architecture for Hearing Aid Applications.

During the break between the two sessions, an evening reception was hosted, which provided a great opportunity for the attendees to share a beer and discuss all the exciting projects and applications.

The second day kicked off with an Emulation Tutorial from Cadence, where Volker Wegner, Sr Principal Application Engineer, highlighted some of the techniques for design and debug using the Cadence® Protium X1 Enterprise Prototyping Platform.

The 3rd session’s talks revolved around Industrial ASIP Applications, where Cologne Chip introduced a new general-purpose FPGA with novel architecture, Dream Chip Technologies presented their Tensilica Vision P6-related project “Structure from Motion” and Videantis presented their Unified visual computing platform, which runs complete embedded vision applications.

During the lunchbreak, the attendees had the opportunity to see some real applications & demos in action. Autonomous driving was the main topic; the attendees got to see Image, Radar and Lidar processing & Neural Networks in action! Cologne Chip’s new general-purpose proposed FPGA and Cadence’s live demos for the Protium debug were presented as well.

The day continued with Tobias G. Noll, Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen, this year’s keynote speaker, giving a perspective on the Next Generation Neuro Science Simulation Systems.

The ASIP Case Studies presented during the event’s 4th & 5th session included a total of 6 speeches from a mixture of academic speakers: Brandenburg University of Technology Cottbus-Senftenberg presented a more adaptive accelerator solution with an approach utilizing the Tensilica Xtensa® LX7 ASIP; LU Hannover introduced a Global Hardware-Based Scheduling in a Multi-Core RTOS on RISC-V; A Latency-optimized Hash-based Digital Signature Accelerator for the Tactile Internet was presented by Vodafone Chair, Mobile Communication Systems, TU Dresden.

The last, but by no means least, case studies included an Application Specific Memory Controller by University of Kaiserslautern, an Application-Specific Soft-Core Vector Processor for Advanced Driver, LU Hannover, and Approximate and Stochastic Computing - opportunities for processing hardware architectures, University of Bremen.

After another year’s successful event, it is only fair to anticipate the new exciting demos and presentations coming next year!

Full agenda, along with all the presentations to be released, can be found here.