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The IEEE Latin-American Test Symposium (LATS) is an annual forum attended by professionals and technologists from all over the world. It is an event where various aspects of system, board, and component testing and fault-tolerance are presented and discussed with design, manufacturing, and field considerations in mind.
This year’s LATS was hosted in Santiago, Chile from March 11-13. The LATS best paper award was written by Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, and Kees Goossens about their collaboration project on cell-aware test. The project is a true testament to the intense cooperation between Cadence, imec, and TU Eindhoven, since the authors are affiliated with two or more of the project partners.
Advanced semiconductor technology nodes have tiny feature sizes, complex transistor architectures and many interconnected layers. This allows integration of an incredible number of devices into a single IC but makes these ‘monster chips’ sensitive to manufacturing defects. Increasingly, such ICs are used in safety-critical applications, such as automotive and healthcare, where defects have profound consequences and test escapes cannot be tolerated. Consequently, there is an industry-wide need for test quality improvement.
Digital logic ICs are designed based on a library of standard cells. Conventional software tools for automatic test pattern generation (ATPG) target faults on the interconnects between cells, such as stuck-at and transition/delay faults. Intra-cell defects are typically not on the radar screen of conventional ATPG tools, and hence only detected fortuitously. Not surprisingly, cell-internal defects are found to cause a significant fraction of test escapes. Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the amount of test escapes compared to conventional ATPG.
The CAT tool flow developed in this project consists of three steps: (1) defect-location identification (DLI), (2) defect characterization based on detailed analog simulation of the cells, and (3) cell-aware ATPG. The award-winning paper focuses on Step 1, as quality and cost are determined by the set of cell-internal defect locations considered in the remainder of the flow. The proposed DLI approach identifies the full set of locations of potential open and short defects in all library cells; however, it passes only a compact set of defect locations to Step 2 of the CAT flow. By filtering out defects with equivalent fault effects, the size of the compact set is only a fraction of the full set, and thereby drastically reduces the defect simulation times without compromising test quality. The paper describes experimental results in which defect stimulation time was reduced from 30 days to 8.6 hours.
It is important to foster an environment of collaboration between industry and academia in order to solve the world’s toughest technological challenges. The tight cooperation between Cadence Modus R&D, imec, and TU Eindhoven continues to advance the state-of-the-art for test and enable higher quality, reliability, and safety for the semiconductors of the future.
Zhan Gao will also present at CDNLive 2019 EMEA at Academic Track. The registration starts now!