Home
  • Products
  • Solutions
  • Support
  • Company

This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Products
  • Solutions
  • Support
  • Company
Community Blogs Academic Network > Cadence Training on imec N2 Pathfinding PDK Unlocks Future…
Vinod Khera
Vinod Khera

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
CDNS - RequestDemo

Discover what makes Cadence a Great Place to Work

Learn About
Cadence Academic Network
Cadence Online Support
imec
imec N2
Pathfinding PDK
P-PDK

Cadence Training on imec N2 Pathfinding PDK Unlocks Future Research

13 Aug 2024 • 4 minute read

Introduction

The semiconductor industry is experiencing significant changes due to the emergence and evolution of new technologies. Innovations like 3D-ICs and advanced power routing techniques are influencing the design of high-performance components such as CPUs and GPUs. However, as the demand for high compute power increases and form factors decrease, it is becoming challenging to achieve sustained performance improvements. Additionally, the limited availability of open process design kits (PDKs) and the gap between academia and industry present further challenges in introducing new PDKs.

In response to these issues, collaborations, such as Cadence and the imec, aim to facilitate innovation and support skills growth in the nano- and microelectronics sectors. In collaboration with imec and Europractice, Cadence recently provided training focused on the digital place-and-route process with the imec N2 pathfinding PDK. This training aims to lower the threshold for future research, providing academia and industry with the tools to train the semiconductor experts of tomorrow. It enables the industry to transition its products into next-generation technologies through meaningful design pathfinding.

Cadence Collaboration with imec

Cadence and imec have a long history of successful collaboration on multiple projects since 2010. Cadence has sponsored a PhD student who spends most of their time on-site at imec.

imec created and validated the Pathfinding PDK (P-PDK) using Cadence's industry-leading AI-driven digital and custom/analog full flows.

Democratizing Access to Advanced Tools and Technology

Foundry PDKs give chip designers access to a library of tested and proven components to deliver functional and reliable designs. These are usually available to the ecosystem once the technology reaches a critical level of manufacturability. However, restricted access and the need for NDAs have created a high threshold for academia and industry to access advanced technology nodes during development.

imec's N2 pathfinding PDK aims to overcome these challenges by providing access to advanced nodes. The imec N2 pathfinding PDK encompasses a comprehensive infrastructure tailored for digital design, featuring a rich library of tested and proven components, including digital standard cell libraries and SRAM IP macros.

However, the ecosystem must have the latest insights into requirements, bottlenecks, and breakthroughs to ensure performance gains with bleeding-edge technology. To keep up with this, imec is collaborating with top EDA companies like Cadence. "Cadence is committed to working with universities and research institutions to drive innovation and support workforce development for the nano- and microelectronics industry," said Yoon Kim, VP of Cadence Academic Network.

Academia and industry are two critical pillars of innovation. In collaboration with imec and EUROCHIP, Cadence conducted a two-day training session focused on the digital place and route process with the imec N2 pathfinding PDK to foster innovation and nurture the semiconductor experts of tomorrow. This workshop, designed to provide hands-on training on advanced node design, was a crucial step in empowering industry professionals and academia.

Training Insights

The session introduces researchers and designers to the PDK and its accompanying libraries, which are structured to serve as a fundamental guide for those interested in developing their IP and encompassing various design phases. The Cadence training focuses on the imec N2 pathfinding PDK for future research endeavors to effectively utilize Cadence tools at advanced nodes. A rapid adoption kit (RAK) developed by Cadence facilitates the substitution of any RTL and the running of identical or altered workflow steps.

This comprehensive workflow, demonstrated through a small design example, covers the synthesis, place and route, timing, and power signoff processes utilizing the imec N2 pathfinding PDK.

The RAK offers a straightforward, modular toolkit alongside a basic framework for conducting placement and routing experiments, focusing on a backside power delivery network (BSPDN). Additionally, the RAK scripts come equipped with commands that present the flow and capture the design quality metrics. A specific script is also provided to run all necessary workflow steps.

The most critical commands in the flow capture metrics relevant to design data, timing information, flow runtime, and memory usage. This functions across various tools and enables the generation of reports in text, HTML, and CSV formats.                       

Machine-readable JSON files are created to compare different runs in a production flow. The resulting reports can then be consistent from run to run. The RAK also includes various reporting commands in the scripts. The imec N2 pathfinding PDK contains standard cells powered from the backside of the die using layers BM0 to BM3, where BM3 is furthest from the die.

Backside power delivery network 

Building the power grid involves several steps. Below are some examples of the relevant commands.

Add the metal stripes

      add_stripes -layer $rules(bm1,name)

     -width $rules(bm1,width)

     -spacing $rules(bm1,spacing)

     -set_to_set_distance [expr 2*$rules(bm1,pitch)]

Add the stripes that connect directly to the standard cells. These are often termed followpins.

      route_special -connect {core_pin}

     -layer_change_range "$rules(bm0,name) $rules(bm0,name)"

     -core_pin_target none 

     -core_pin_layer "$rules(bm0,name)"

 Add vias between the various layers

     update_power_vias -add_vias true

    -bottom_layer $rules(bm1,name)

    -top_layer $rules(bm0,name)

The various flow steps save timing information in text and binary format and can be loaded in the tool GUI, allowing cross-probing of the reports, layout, SDC, and schematic.

Please visit the Cadence Learning and Support Portal for more details about implementing the digital place and route flow for a small IP using the imec N2 pathfinding PDK.

Read More

  • Cadence Accelerates System Innovation with Breakthrough Integrity 3D-IC Platform
  • imec and Cadence Tape Out Industry's First 3nm Test Chip
  • 3nm Cadence and imec
  • Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now Shipping in Modus DFT Software Solution

CDNS - RequestDemo

Have a question? Need more information?

Contact Us

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information