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At CDNLive EMEA, Zhan Gao presented her results on cell-aware test. This is the paper she presented at the Latin American Test Symposium (LATS) in Santiago, Chile in March and won the Best Paper award there (see Anton's post on the Academic Network blog Best Paper Award at LATS2019 for Zhan Gao for more details). She presented an earlier version of the paper at CDNLive EMEA last year (see CDNLive: Testing Times in Munich for details).
Also attending CDNLive was imec's Erik Jan Marinissen, who supervizes Zhan's research. Her work is a great example of cooperation between imec, Cadence, and academia. In this case, the Technical University of Eindhoven where Zhan is a PhD student starting her final year.
I wrote about a similar example of three-way cooperation a couple of years ago in CDNLive: Design Technology Co-Optimization for N7 and N5. Luca Matti did his PhD on DTCO, design technology co-optimization, at TU Braunschweig, while working for Cadence and doing much of his work on-site at imec.
Also involved in the cell-aware test project in the past were Joe Swenton, who works for Cadence in New York, and Santosh Malagi, who works for Cadence in Noida India.
I was asked to interview Erik Jan for a video, discussing Cadence's cooperation with imec, and cell-aware test in particular. Here is the video:
Zhan also presented her work for a video, which you can see here:
The basic idea of cell-aware test (CAT) is to go beyond the traditional gate-level stuck-at-X models, which only look at the inputs and outputs of library cells. CAT looks inside the cells and inspects the layout, looking for potential shorts and opens. Obviously, a short can only occur between two pieces of interconnect if they are adjacent. An open can only occur between two nodes if they are joined by some interconnect. Zhan's approach uses circuit extraction to identify these nodes rather than inspecting the layout directly. Two nodes that have a lot of capacitance between them are (probably) close and so might short. Two nodes that have a high resistance between them are joined but with the possibility of an open occurring. Additional vectors can then be added to the test sequence, if required, to ensure that these faults will be observable if they occur. Zhan's work makes generating all this data and making use of it computationally tractable. The diagram above summarizes the flow.
CAT operates in three phases. In phase 1A (which is done once per library), the extraction is done to identify the potential layout dependent defects. In phase 1B, also once per library, vectors are identified to detect these faults. These are optimized (since a vector created to detect one fault may also identify many others) to create the DDMs, the default detection matrices. This data is then used in creating the vectors for each design, adding appropriate vectors for each library cell instantiated in the chip.
The basic approach was described in my post from CDNLive EMEA last year that I referenced above. This year, Zhan had taken the approach and applied it to a 3nm library, the most advanced library that imec has created in their iN5 process (yes, the numbers used for process nodes are confusing). The iN5 process has some additional complexity since it has buried power rails and a local interconnect layer known as MINT (see the diagram).
This program is a great example of cooperation between academia (TU/e), a research institute (imec), and Cadence. The fact that Zhan's name in the title of the paper is followed by 1,2,3 is part of the evidence: she works at all three organizations.
One criticism of some academic research is that it is too academic: it produces papers and theses, but is impractical in the real world. However, this research is a great example of combining the best of all worlds so that the ideas get incorporated into a real industrial product and see immediate use on real designs.
The results of the research have been incorporated into Cadence's Modus DFT Software Solution. As it happened, the release containing the technology was shipped just a few days after CDNLive and the video interviews.
The big show in test is the IEEE International Test Conference, or ITC as it is normally known. It used to always be at the Disneyland Hotel in Anaheim, which was perfect for finding amusing opening sentences for blog posts, but for several years it has been in Washington DC, which is almost as perfect. It takes place in the Marriott Wardman Park from November 12 to 14. Note: this hotel used to be the Sheraton. You don't need me to tell you that there are lots of things to see in DC. My personal favorites are the Smithsonian Air and Space Museum, and the Vietnam Veterans Memorial. I discovered years ago when I had jet-lag and was awake early that it is great to see as it is getting light when I was the only person there. It is open 24 hours a day.
Since this will be the 50th anniversary of the conference, there will be special sessions looking back at 50 years of test. I'm sure some famous names will be reminiscing. It is still too early for a full schedule to have been published.
Cadence will be there, so come by and find out about Modus DFT, cell-aware test, and our other test solutions.
For more information, see the Cadence Modus DFT Software Solution product page. Or, for a more academic take, read the paper Defect-Location Identification for Cell-Aware Test presented at LATS'19 in Chile.
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