Digital Design and Signoff Training Deep Dive: Part 1 – Synthesis and Test

This blog series will the break down the top 15 Online Training courses among students and professors into their different technical areas and share the supporting courses that go along with them, starting with Digital Design and Signoff. Designs are getting bigger and more complex, this translates to more challenging power, performance, and area (PPA) targets. We want you to become a Design pro, so we’re going to share the Cadence Online Training courses you should take to learn these tools.

We’ll start by covering Synthesis and Test. Cadence synthesis solutions provide an integrated flow that balances the growing need to understand the architectural-level abstraction of the design alongside the detailed physical implementation constraints.

We’re pulling the recommended training flow from the Learning Maps, which structure the Cadence Online Training courses into technical areas and difficulty levels. Some of the below courses offer a Digital Badge, once earned, you can showcase that you’re Cadence Certified on your resume, email signature, and across social channels like LinkedIn.

Summary

	1.	Basic Static Timing Analysis*
	2.	Genus Synthesis Solution with Stylus Common UI*
	3.	Fundamentals of IEEE1801 Low Power Specification
	4.	Low-Power Synthesis Flow with Genus Stylus Common UI
	5.	Design for Test Fundamentals
	6.	Test Synthesis with Genus Stylus Common UI
	7.	Advanced Synthesis with Genus Stylus Common UI

*One of the top courses among students and professors

Basic Static Timing Analysis

In this course, you learn the basic concepts of static timing analysis and apply them to constrain a design. You apply these concepts to set constraints, calculate slack values for different path types, identify timing problems, and analyze reports generated by static timing analysis tools.

After completing this course, you will be able to:

• Identify:
  • Timing arc information from a library, including unateness, delays, and slew
  • cell delays from a library and calculate output slew degradation
  • properties of a clock, including period, edges, slew, and duty cycle
  • timing path types and calculate slack values
• Set:
  • Design-level and environmental constraints
  • Timing constraints, including clocks and external delays
  • Path exceptions
• Learn more!

Genus Synthesis Solution with Stylus Common UI

In this course, you learn about the features of the Cadence Genus Synthesis Solution with Stylus Common UI with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture-level PPA) and how SoC design productivity gap is filled by Genus. You also learn how to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using the Stylus Common UI.

After completing this course, you will be able to:

• Explore:
  • Features of the Genus Stylus Common User Interface
  • MMMC and how to set up and update the MMMC configuration of a design
  • Flowkit and Unified Metrics
• Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
• Optimize designs using the physical synthesis flow
• Learn more!

Fundamentals of IEEE1801 Low Power Specification

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low power specification format concepts. You also explore how power intent information can be used for a design across various stages of flow such as functional verification, synthesis, logic equivalency checking, place and route, test, timing signoff, power integrity and so forth using Cadence tools.

After completing this course, you will learn:

• Concepts of:
  • Low Power
  • Hierarchical UPF
  • Retention, Isolation and Level Shifter Strategy
  • Evolution of IEEE 1801
  • Power Supply Network (PSN), Power State, Power Domain Interface
• Explore
  • IEEE Low Power Strategies
  • 1801 Concepts
  • Cadence Tools Supporting IEEE 1801
• Learn more!

Low-Power Synthesis Flow with Genus Stylus Common UI

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis.

After completing this course, you will be able to:

• Run:
  • Low-power synthesis flow
  • Optimizations to reduce dynamic and leakage power consumption
• Analyze:
  • Power reduction techniques
  • Power results
  • Low-power design with Conformal® software
• Learn more!

Design for Test Fundamentals

This course is an introduction to the concepts and terminology of Automatic Test Pattern Generation (ATPG) and Digital IC Test.

After completing this course, you will be able to:

Understand and be able to discuss why we test, what we test, and how we test, including:

• Basic DFT design rules
• Basic diagnostics capabilities
• Learn more!

Test Synthesis with Genus Stylus Common UI

In this course, you learn to use Genus Synthesis Solution in Stylus Common UI mode to insert test structures in your design. You learn how to set up constrains, generate various reports and interface with other tools, and explore various troubleshooting scenarios.

After completing this course, you will be able to:

• Run
  • DFT rule checker and fix DFT violations
  • Hierarchical scan insertion
  • Advanced testability features, boundary scan, PMBIST, Compression and OPCG
• Set up:
  • Constraints for the design for testability (DFT)
  • DFT configuration constraints and preview scan chains
• Learn more!

Advanced Synthesis with Genus Stylus Common UI

In this course, you use Genus Synthesis Solution in Stylus Common UI mode to debug problems in the synthesis of complex designs when optimizing for timing, area, and power. This course includes problem scenarios that you typically encounter in a synthesis flow and how you can debug them. You also learn to use the synthesis flow to achieve better quality of results for the place-and-route tools.

After completing this course, you will be able to:

• Identify:
  • Features of the Cadence Genus Synthesis Solution
  • Best practices for synthesizing complex designs
  • Setup for Genus Physical
  • Interface Logic Model
  • Multi-Mode Multi-Corner (MMMC) flow
• Apply:
  • Retiming to fix the timing of a complex block
  • Multi-Bit Cell Inferencing
• Analyze:
  • Physical Synthesis results
  • Log file to debug and fix the timing of a design
• Verify designs using Conformal Equivalence Checker
• Learn more!

After completing these industry grade courses, you’ll have a better understanding of Genus Synthesis Solutions, for not only synthesis capabilities but also for test structures. You’ll be one-step closer to mastering Digital Design and Signoff solutions. Stay tuned for upcoming blogs that’ll further explore the Online Training courses available!

How to enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk