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Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical cell views for timing, power and signal integrity, accounting for process variability, managing leakage power, and hitting a low power budget make obtaining market leading performance extremely difficult.
To overcome these increasing burdens, designers have to reduce margins that exist within timing models provided by a 3rd party IP provider or a central library group. This will require designers to control how standard cell library views are created to better tune their models. The best way to do so is to characterize/re-characterize the library for specific design goals.
Today, designers working on production designs for 40nm, 28-nm and 20nm processes are left with no window to work with - and the situation will only get worse as we head towards 16nm and 14nm. For example, timing signoff can be achieved at the worst case corner at high temperature but not at low temperature. The need for supporting a wide range of process, voltage and temperature corners (PVTs) is increasing due to shrinking device geometries. The impact of variation and temperature inversion is greater for lower voltages, yet these are now the norm due to the need to reduce power.
The sensitivity to process variation, the exponential growth of characterization runs, and the number of data points per each characterization run pose more challenges. The paradox is that the overlying process technology can often deliver on the design goals but the tools, process models and methodology get in the way. Every tool and each modeling level adds margin until all the guard bands eat up all the design space.
The following areas need careful consideration due to their impact on library accuracy and development schedules:
1. Standard cell library characterization solution must offer high productivity for large complex cells and complex I/Os
2. Solution must support libraries from multiple foundries and IP providers
3. Solution must be tightly integrated with a leading edge simulation solution for uncompromised accuracy and scalable performance
4. Solution must support a wide range of PVTs
5. Solution must support low-power, high speed standard cell library variants
6. Generated models must be of utmost precision and accuracy
7. Models must be consistent with other characterization components including large macros and memory blocks
8. Solution offers flexibility in setting measurements and thresholds for items such as:
a. Setup and hold for flip-flops, latches and clock gating cells b. Pin capacitance measurement c. Type of pre-driver used
An integrated library characterization solution based on the Cadence Virtuoso platform is depicted below.
By characterizing standard cell libraries, users can get a wide range of choices for how simulation data is captured and measured before it is encapsulated in Liberty format. For example, the value of pin capacitance varies by up to 50% depending on the measurement thresholds and this can have a major impact on hold time closure. For setup and hold values, typically there is additional margin added by the IP provider to avoid warnings further down in the tool flow. For example, some tools do not support negative setup or hold times so margin is added to the library to remove the negative constraints.
For designs that use multiple voltages or dynamic voltage scaling, the delay calculator will use interpolation if the library views do not explicitly cover the voltage being used, nearly always providing pessimistic results. Designers can overcome this by characterizing more voltage corners which reduces built-in margins thus achieving higher accuracy. Moreover, by the time the library is delivered the process models used to create it may have changed. Process models typically tighten their margins as they mature, but if the library isn't up to date, the timing closure tools will not enjoy this benefit and will continue to be over-constrained.
For memory IP blocks, the timing and power models are created by a compiler without knowing the exact context of how the memory block will be used. The memory compiler creates the model for each instance from fitting data derived from the characterization of a small set of memory instances. A more accurate model can be achieved by characterizing the exact size for each instance of each memory block using precise loading, slew rates, voltage and temperature values for each design.
The investment required to do project or design family specific characterization is relatively small. A new library corner for a thousand cells can now be completed in half a day or less using a single eight core machine. Smart characterization tools exist that can automatically setup and optimize the characterization directly from analyzing the transistors and arcs inside the cell. Besides, this allows design teams to take control of the standard cell library delivery schedule so they do not need to rely on the over-burdened central group or to pay additional fees if a new corner or a different characterization setting is required.
Margins are necessary to help safe guard against inaccuracies inherent in abstracting silicon components to the higher models. However, over-margining is creating a huge barrier to the effective use of 45nm and below processes. Using statistical methods will greatly help by providing a more realistic timing answer, but also taking control of the margins inherent in off-the-shelf IP models can also alleviate many timing closure challenges. To accelerate their development schedules, designers should take control of their characterization tasks to create realistic library views instead of relying on over-margined standard cell libraries.