Analog Circuit Modeling Using Verilog-A within Virtuoso: A Video Series

Modeling an analog circuit in Verilog-A is about writing equations that describe its behavior, followed by simulating the model and checking the results. Generating the correct output requires understanding how the equations relate to actual circuit behavior, which is a challenging gap.

This video series addresses that gap. It relates modeling constructs to specific circuit operation and how these implementations simulate. By establishing a clear connection between circuit operations and Verilog-A implementations, the series enables a more intuitive and structured understanding of behavioral modeling.

Device Modeling: Equations Describe Circuit Behavior

To understand how Verilog-A models device behavior, begin with the diode example from Modeling a Diode using Verilog-A in Virtuoso (Video).

A diode is a device in which the current increases exponentially under a forward-bias condition.

When implementing the equation in Verilog-A, using the standard exponential function (exp(x)) can create numerical issues when the input value becomes large, leading to convergence problems during simulation. The Verilog-A operator limexp(x) can be used as a substitute with better convergence properties:

(limexp((V(p,n) - (rs * I(p,n)))/$vt) – 1)

Data Converters

Let us consider the design of a 4-bit DAC using Verilog-A. In DAC modeling, although the input is digital, the analog domain requires these abstract logic levels to be represented as continuous quantities, such as voltages. Logic states are determined from voltage levels by defining a threshold value. For example, if the threshold is 2.5V, any input voltage above this level is a logical ‘1,’ and anything below that is a logical ‘0.’

Once the logic levels are determined, binary weighting, where each input bit contributes a value based on its position, determines the input. For a 4-bit input d₃d₂d₁d₀, each bit corresponds to binary weights of 8, 4, 2, and 1, respectively. By adding these weighted contributions together, the digital value translates to an equivalent analog voltage.

Refer to the links below for a complete understanding of data converters modeling in Verilog-A:

Modeling a Digital-to-Analog Converter using Verilog-A in Virtuoso (Video)

Modeling an Analog-to-Digital Converter using Verilog-A in Virtuoso (Video)

Generators: Time-Based Signal Generation

To understand how signals are generated based on time in Verilog-A, refer to the videos:

Modeling a Square Wave Generator using Verilog-A in Virtuoso (Video)

Modeling a Swept Sine Source using Verilog-A in Virtuoso (Video)

Signal generation is a time-controlled process, where the output waveform is based on its variation with time. Consider the square wave generator modeling video. A square wave is a periodic signal that alternates between two voltage levels over a time period, switching the output voltage levels at regular time intervals.

The following Verilog-A expression represents the switching behavior of a square wave generator:

@(timer(tdelay, period/2)) x = !x

The @timer() operator first triggers an event, and after an initial delay (tdelay) it repeats the event at fixed intervals (period/2). At each event, the variable ‘x’ toggles its state (x = !x), thereby switching the output between two levels. The periodic switching directly results in the generation of square waveforms.

Digital Device Modeling in Verilog-A

For a clear understanding of how edge-triggered digital elements are modeled in Verilog-A, refer to the video:

Modeling a D Flip Flop using Verilog-A in Virtuoso (Video)

In this video, the D flip-flop demonstrates edge-triggered behavior. A D flip-flop is a digital storage element that captures the input data at a clock edge and holds that value until the next clock edge.

To implement the edge-triggered behavior in Verilog-A, it is necessary to detect the exact instant at which the clock edge occurs. The @cross() operator detects when a signal crosses a defined threshold:

@(cross(V(vclk) - vtrans_clk, +1))

In the above expression, V(vclk) represents the clock signal and vtrans_clk represents the threshold level used to define the switching point. The ‘+1’ argument specifies that the event is only when the signal crosses the threshold in a positive direction, i.e., during the rising edge of the clock. Thus, the Verilog-A expression ensures that an event occurs precisely at the rising edge of the clock signal.

Explore the Complete Series

From device-level behavior to data conversion, time-based signal generation, and digital device modeling, each example in this series forms a complete understanding of behavioral modeling in Verilog-A.

This blog provides an overview, but the complete depth, along with detailed explanations, step-by-step implementations, and simulation results, is available in this video series.

Explore the videos below to gain a deeper and practical understanding of analog circuit modeling using Verilog-A.

Modeling an Operational Transconductance Amplifier using Verilog-A in Virtuoso (Video)

Modeling an Analog Bus using Verilog-A in Virtuoso (Video)

Modeling a Phase Detector using Verilog-A in Virtuoso (Video)

Modeling Transfer Functions with Laplace Filter Expressions using Verilog A in Virtuoso (Video)

Modeling a Sampling Function Block with Z-transform Operators using Verilog-A in Virtuoso (Video)

Additional models and detailed explanations are available on the support page for further exploration: Cadence Learning and Support Portal

Related Resources

Online Course

Analog Modeling with Verilog-A Course

Become Cadence Certified

You can become Cadence Certified once you complete the course and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal.

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
• You will need an email address and host ID to sign up.
• If you need help with registration, contact support@cadence.com.

To stay up to date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

For more information on Cadence circuit design products and services, visit www.cadence.com.

Take the Accelerated Way

The faster you finish your online training, the sooner you can claim your Digital Badge. Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. This is just the beginning. We're regularly adding new Accelerated Learning titles.

Accelerated Learning courses are marked with this symbol  in our Learning Maps.