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The FinFET device architecture, which is currently a major trend in advanced node process technologies, has advantages such as high drivability and low leakage current. However, it has significant manufacturing constraints—including the fact that the devices can be placed along only a single direction and cannot be rotated. The layout design must satisfy many requirements that have not existed in previous technologies, and this work becomes very time-consuming for layout designers.
We heard a story about these thorny problems—efforts to construct the design environment for FINFET devices, the solutions built by Toshiba Memory Corporation—from Mr. Kazuhiro Oda, Chief Specialist at Toshiba Memory Corporation. Mr. Oda has made many breakthroughs for building several design environment infrastructures. Hiroshi Ishikawa, Senior Engineering Manager at Cadence, recently interviewed Mr. Oda.
Mr. Kazuhiro OdaChief Specialist, System Core Technology Development Dept. 2, System Technology Research & Development Center, Toshiba Memory Corporation
—FinFET became the primary device structure upward of 16nm / 14nm. How has your company’s design style at your site been affected since the FinFET technology was selected?
Oda: Increasing the complexity of the design rules affected the productivity of the layout-creation phase.
FinFET device technology only allows one to change device sizes discretely by number of fins. We made a guideline and standardized the transistor length so that it fell into two sizes, and the transistor width fell into one size. As a result, we successfully simplified the layout work, since abutting devices was easily done.
FinFET devices can carry larger current per area than planer CMOS. Although it is good that the device can drive larger currents, problems such as electro-migration (EM) and the self-heating-effect (SHE) often occurs around the device.
However, we avoided unnecessary iterations by using our guidelines and the design checks within the internal utility programs at the design phase.
Until now, we had directed the logic designers to perform the logic simulations with the Cadence Spectre Circuit Simulator while estimating the parasitic capacitance and resistance for the projects. We would forward the data to the layout development side. By doing so, we completed the layout design relatively easily. However, this was not the ultimate—or perfect—solution. The problems we observed were inconsistencies of the estimation of the parasitic capacitance and resistance by each engineer.
To help to resolve this problem, a Cadence application engineer helped with the insertion of dummy cells to mitigate the SHE in the layout. Using the Virtuoso Layout Suite for Electrically Aware Design (EAD) and this utility, we successfully completed our design on time.
― In addition to EM and SHE’s, what kind of challenges do you foresee in future design work with advanced node technologies?
Oda: We cannot ignore the delay of routing channels due to increasing minimization. A design correction is inevitably required for the circuit to operate at high speeds. To minimize the work for correction, I feel a design flow with parasitic-aware design (PAD) and EAD will be essential.
Also, for routing, with the self-aligned double patterning (SADP) technology, a wire cannot be “bent”. Width-spacing patterns (WSP) are a key to grow layout designer efficiency. Understandably, by defining a routing grid that does not violate the design rules, the time for the design rule corrections after routing can be improved. It is important, I believe, to migrate from the stage of correcting new errors quickly into the stage of building a system that does not allow the creation of errors.
All errors in a design need to be fixed at some stage. So, as we all know, correcting them as they occur, instead of deferring the fixes until later, can be effective for reducing the development period. However, what I suggest is one step ahead: build an environment so that the errors cannot be created in the first place; that is, realizing a design without errors.
―What kind of challenges throughout design flow did you find when you used the technology with FinFET devices?
Oda: This is pertinent to the design flow with not only FinFET-based designs but also any advanced-node technologies. We are no longer able to disconnect the design flow between the logic design stage and the layout design stage. A logic design engineer (front-end engineer) and a layout design engineer (back-end engineer) need to collaborate closely to complete the design. But this is quite challenging. For that reason, it is indispensable to make decent guidelines. Also, it is essential to have a mechanism, constraint-driven layout, which the Virtuoso platform offers, that stores and delivers the mandatory requirements in a logic design to a layout designer.
Generally speaking, I think the efficiency improvement for the entire design process is extremely difficult without considering the logic design the final layout. This is why Virtuoso ICADV12.3’s front-end (FE) through back-end (BE) total solution is indispensable for advanced node designs.
―Finally, do you have any comments for Cadence?
Oda: For now, I hope Cadence continues to develop tools that make the engineers who are actually designing comment with astonishment, “Aha, we wanted these features!”
ArticlePress / Interviewer: Hiroshi Ishikawa, Cadence