Connectivity and Constraint Driven Design: Will It Ever Become The Standard for Custom IC / Analog Design?

In the late 70's and early 80's system level PCB and Digital IC physical design evolved from manual Rubylith and Digitizing methods. If I haven't dated myself already with the terms Rubylith and Digitizing I know that I'll really be dating myself with my history at IBM.  While working for IBM in the General Products Division San Jose, CA during this period of time I used an IBM proprietary EDA application and database named IGS (Interactive Graphics System) which was developed and supported by IBM's EDS (Engineering Design System) group in Poughkeepsie, N.Y. I first used an old vintage 1965 IBM 1130 computer with a monochrome IBM 2250 Graphical Display Unit that supported a screen light pen and LPFK (Lighted Program Function Key) pad. The IBM 1130 system had a binary switch control panel, and options such as a punch card and punch tape reader/writer for data archiving, an IBM 1403 ‘Greenbar' line printer and IBM 2314 Disk Cartridge that was a vary large single plate removable device. A few years later IBM's IGSII came out using the new IBM 5080 color graphics display with pen tablet and LPFK (Lighted Program Function Key) pad mated to an IBM mainframe and disk farm. I was in layout heaven! And no that's not me in either picture!

                  IBM 1130 and IBM 2250 Monochrome Display    

                              IBM 5080 Color Display and Peripherals

The 1980's - PCB and Digital IC Connectivity and Constraint Driven Physical Design

In parallel, during the 80's the new EDA industry and its member companies started to emerge and sell commercial non-proprietary EDA CAD systems for PCB and Digital IC design to electronic design and semi-conductor companies. The emergence of these new EDA companies and tools resulted in rapid advancement of exciting new solutions for the design of PCB and Digital IC's. With the increase in the number of components, transistors, interconnect, number of process layers, and increased number and complexity of design constraints and process rules an exciting new evolution in PCB and IC design was introduced, Connectivity and Constraint Driven layout or more commonly referred to as ‘SDL' (Schematic Driven Layout). Even IBM entered the connectivity and constraint driven world with its proprietary NL1 (Net List) predecessor to IGS II with an application named CCDS (Custom Card Design System). IBM also entered the commercial non-proprietary PCB layout market with CBDS (Circuit Board Design System) a Bell Northern Research OEM product that supported SDL along with ViewLogic schematic and simulation tools which I used and supported when I worked for IBM in my early EDA career.

With these new exciting PCB and Digital IC design tools and flows schematics or net lists could now be created with dynamic links between the logical and physical design data and component libraries. This enabled higher levels of automated and automatic solutions such as placement, routing and design constraint and process rule checking to be supported. The customer validated benefits of adopting the connectivity and constraint driven tools and flows were improved productivity, reduced time-to-market and better quality-of-results. And yes, there was some overhead and pain involved in adopting these new tools and flows but, in the end the aforementioned benefits outweighed the overhead and pain. Today the majority, if not all, current PCB and Digital IC physical layout designers have adopted the connectivity and constraint driven tools and flows while achieving the aforementioned benefits.

                 Cadence Allegro PCB Design

   Cadence Encounter Digital Implementation System

The 1990's -  Custom IC / Analog Connectivity and Constraint Driven Physical Design

In the mid- to late 90's EDA companies attempted a similar evolution of Custom IC / Analog tools and flows to support SDL design with the introduction of Cadence's ACPD (Automated Custom Physical Design) suite of tools including Virtuoso Composer, Virtuoso XL, Virtuoso Custom Placer and Virtuoso Custom Router which came from the IC Craftsman suite of IC design tools acquired during the Cooper & Chyan Technology acquisition and merger. Other EDA companies attempted to follow suite with their own ‘ACPD' solutions.  These new Custom IC / Analog design tools were marketed and customer validated to achieve the same benefits that were assigned to the PCB and Digital IC design tools: improved productivity, reduced time-to-market and better quality of results.

The New Decade - Virtuoso Layout Suite XL and GXL

In the new decade of 2000 connectivity and constraint driven design solutions for Custom IC / Analog design have continued to evolve with floor-planners, area and cell based placers, constraint driven layout synthesis, interactive assisted and automatic routing, process migration and advanced process node support with DFM optimization. The new Virtuoso Layout Suite XL and GXL products continue in the legacy of the ACPD suite of tools and flow providing a rich and comprehensive set of advanced custom IC / Analog design tools that are customer validated to deliver the same benefits of improved productivity, reduced time-to market and better quality of results for today's complex advanced process node designs.

          Virtuoso Analog Design Environment   

                Virtuoso Layout Suite GXL

The Adoption Dilemma

In light of the mass adoption and success of the connectivity and constraint driven tool sets and flows by the PCB and Digital IC design community and the availability of similar Custom IC / Analog tools one would think that the Custom IC / Analog design community would have the same level of adoption and success with these tools as a standard layout design solution. However, this does not seem to be the case even after a decade of tool and flow availability. The majority of Custom IC / Analog designers still choose to use the tried and true manual method of ‘polygon pushing'. Custom IC Layout Designers use the legacy Virtuoso LE or new Virtuoso Layout Suite L tier of tools to artfully but manually and tediously create and edit their Custom IC / Analog designs. The manual ‘L tier' process includes creating and editing polygons manually with non-connectivity based assisted automation, hard-copy or non-linked CAD schematics for logical connectivity, process rule books for DRC control, verbal or written design constraints, and manually measuring and checking and/or iteratively using LVS and PV verification tools to validate the logical and physical correctness of the design. Without automated management and checking of connectivity, design constraints and process rules higher levels of automation (e.g. placement, routing, constraint enforcement) found in the VLS XL and GXL product tiers cannot be enabled and leveraged. As a result of this lack of enablement the benefits of improved productivity, reduced time-to-market and better quality of results seen by PCB and Digital IC designers for over two decades cannot be achieved.

Why? - Your Opinion Counts!

So will we ever see the connectivity. design constraint. and process rule driven VLS XL and VLS GXL tier tools and flows adopted as a standard by the Custom IC / Analog design community? What will it take to achieve this? What are the inhibitors and roadblocks to adoption of these tools and flows? Can future advanced node Custom IC / Analog designs be completed successfully and within the bounds of expedited design schedules, product market windows and with first tape out quality of results without them? As the saying goes, "Time will tell" but, in the meantime I welcome your thoughts on this blog topic as we wait.

Stay tuned to my future weekly blogs as I overview the VLS XL and GXL advanced connectivity and constraint design features and flows including the potential benefits of each that can be achieved with their use versus traditional ‘polygon pushing' methods.

Craig Thompson