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The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we will explore the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creating these IC designs, by maximizing speed and silicon accuracy throughout the design process. The methodology also covers the key design domains of analog, custom digital, and RF, and supports their integration with digital standard cell blocks.
The traditional methodology for performing mixed-signal designs used to start at the transistor level and then moved up in the design hierarchy. This led to limited visibility to the top-level layout requirements. The current design methodology involves the top-level and lower-level of the designs to start simultaneously and proceed concurrently. This is to produce a “meet-in-the-middle” approach. It is this approach that balances the need for speed and silicon accuracy, ultimately producing a predictable schedule and first-pass success. This Custom IC Design methodology can be applied to a complex integration or a particular domain area. Each domain applies the meet-in-the-middle approach, combining top-down speed with bottom-up silicon accuracy.
Top-level designs begin with high-level abstract description and lower-level designs are performed at the transistor or behavioral level. These high-abstraction level blocks are then gradually replaced with more accurate transistor-level views, as and when they are available from the block designers.
The following figure illustrates the 5 key design stages in the Custom IC design methodology and the tools used to execute them:
We have created a series of Rapid Adoption Kits (RAKs) on Custom IC design methodology flow that will enable you to try out each of these stages. These RAKs are based on a Flash ADC design and use various Cadence tools to perform the design tasks. At the very top-level, mixed signal simulations are performed. The Flash ADC contains an ADC Sample and Hold block, Comparator and Reference ladder block for the analog/behavioral level simulation.
ADC Flash Top Level Design
In this series of RAKs, each stage as mentioned in the Design Flow Stages above is explained in detail. It starts with schematic and layout design of the Sample and Hold ADC block, then a pre-layout simulation is run. Extraction is performed on each of the individual blocks inside the top-level Flash ADC design, then a final post-layout simulation analysis is performed to ensure the pre and post-layout results are consistent. The GDSII (Graphic Database System II) file is created as a final step, which can then be sent to the foundry for fabrication/manufacturing of the chip. You can run each stage in the RAK independently, or work your way through the entire flow.
In the next blog, we will talk about the first stage of the flow, the Schematic Capture and Circuit Simulation stage.
To try out the Custom IC Design flow, you can download the RAKs from the Cadence Learning and Support website.
For more information on Cadence Custom IC circuit design products and services, visit www.cadence.com.
Virtuoso Schematic Editor User Guide
Virtuoso ADE Assembler User Guide
Spectre Classic Simulator, Spectre APS, Spectre X, and Spectre XPS User Guide
Virtuoso Layout Suite XL User Guide
Virtuoso IPVS User Guide
Quantus Extraction Users Manual
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Happy reading, and stay safe!
Ashish Patni, Sanjay Gupta, Harsh Gupta
Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more.