Early, Accurate, and Faster Exploration and Debug of Worst-Case Design Failures with ML-Based Spectre FMC Analysis

Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. However, using smaller transistors increases complexity and poses many challenges for IC design engineers. At advanced nodes, it is very challenging to ensure a high yield due to large process variations. Primarily, yield helps to determine profitability and shows a clear picture of the quality, so it plays a critical role in semiconductor manufacturing. The purpose of aggressive process scaling is only met if a high yield is ensured and verified. IC designers use Monte Carlo (MC) simulations to find the worst-case design failures and estimate the yield before mass production. This method attains accuracy at the cost of long run-time for analog simulations. With the shrinking time-to-market windows, can we afford to run millions or even billions of statistical simulations and spend so much time on verification?

Cadence Spectre FMC analysis uses machine learning (ML) and advanced statistical techniques to enable early, accurate, and significantly faster yield estimation than traditional brute-force Monte Carlo simulations.

Challenges in Finding and Fixing Rare High-Sigma Design Failures

Semiconductor foundries capture the device-level variations accurately as statistical models. This has facilitated the adoption of variation-aware design methodologies to ensure a low probability of IC failures due to random variation effects. Monte Carlo (MC) simulations leverage these statistical models to determine the worst-case samples and ensure the target yield. However, MC simulations require significant computing resources and time, especially for design blocks used repeatedly on the chip with a low probability of failure, such as standard cells, memory bit cells, and analog IPs (ADCs, DACs, PLLs, Bandgaps).

Even with the increased performance of simulation tools and the availability of large-scale computing resources (more cores and cloud computing), it is impractical and, in many cases, impossible to perform these computationally intensive MC simulations. It is especially true for high-sigma MC analysis, where the number of MC simulations needed can exceed a billion runs to ensure a high yield. Even when the number of simulations is small, each simulation is expensive.  

Another important aspect is the constantly shrinking time-to-market. he traditional schemes take a long time to find the worst-case samples as they involve lots of unnecessary simulations around the mean to get to the valuable tail information of the Gaussian distribution. For example, the standard MC simulations for 6-sigma analysis need ~31 CPU years to find the worst-case samples in 1 billion samples (assuming each simulation takes 1 second).

Figure 1: Limitation of using traditional brute force Monte Carlo simulation

So, applications like autonomous driving, healthcare, HPC, AI, and IoTs can no longer rely on traditional schemes such as MC analysis. The semiconductor industry needs a tool to accurately estimate the yield and detect the worst-case samples with fewer simulations and less time in determining the high-sigma failures.

Figure 2:  Lots of unnecessary simulations around mean to get to the valuable tail information

So, EDA solutions using state-of-the-art simulator technologies and methodologies that enable fast (minimum number of simulations) and accurate high-sigma Monte Carlo analysis are essential.

Solution: Cadence Spectre FMC Analysis

To overcome the challenges mentioned above, Cadence integrated Fast Monte Carlo (FMC) technology into the well-known and industry-leading Spectre Simulation Platform, widely adopted as the golden standard for high-performance SPICE-accurate circuit simulation.

Spectre FMC analysis applies to 3-6+ σ applications, including memory/Bit/Std cells, analog/mixed-signal, RF, and I/O blocks. It combines ML and advanced statistical techniques to

• Estimate the yield early and faster without compromising statistical accuracy
• Find the worst-case samples with fewer simulations, allowing a user to extract useful statistical information without running the full set of MC samples

Spectre FMC Analysis enables the command line use model and the Virtuoso ADE suite use models. Analog designers using the Virtuoso ADE suite can run the Spectre FMC analysis from the same environment and use its productive and easy-to-use analysis and debug features.

Figure 3: Spectre FMC and design applications

Virtuoso ADE suite can also be leveraged for distributed processing of Monte Carlo simulations across a compute farm or cloud. The key technologies and features are:

High-sigma Monte Carlo analysis to identify worst-case circuit behavior

We need more simulation cycles to determine the worst-case samples in the low-probability regions. Spectre FMC Analysis overcomes this using ML and advanced statistics-based accurate estimation of failures and yield. It Identifies the worst-case samples, and based on the number of statistical variables and the number of devices in the circuit or design under test (DUT), the speedup observed is from 10X to more than 10,000X.

Integration with characterization and static timing flows

• Enabling faster LVF generation in Liberate Trio Characterization Suite, as it generates .Lib files in orders of magnitude less time with FMC analysis.
• Tempus: The semiconductor industry needs a reliable high-sigma sign-off solution to both accurately identify the worst-case samples causing circuit functionality failures and estimate yield uncertainty with a minimal overall number of simulations and turnaround time. Tempus integration enables faster static timing analysis (STA) and signoff of critical path delays affected by statistical variations.

Yield estimation capability

• Determine the yield of the circuit with a user-defined fixed cost of simulations
• Provides a faster answer for yield with the limited simulation budget before getting into the fine-tuned analysis of the worst-case failures through Monte Carlo simulations

These key technologies and features help estimate yield and detect the worst-case samples with fewer simulations.

Case Study: 5nm PLL Post-Layout Verification

To showcase the benefits of Spectre FMC Analysis in advanced node design, we have considered a 5nm phase-locked loop (PLL) design. PLLs are among the most widely used analog circuit blocks and are an important part of most large-scale digital and analog, mixed-signal systems. For instance, PLLs are used in clock generators, SerDes, etc. PLL has a longer gate-accurate simulation time and involves many MC simulations that may affect the yield. Further, the post-layout analysis involves the parasitics resulting in a longer simulation time. The Spectre FMC Analysis algorithm can accurately predict the worst-case samples in fewer simulation cycles, as in Figure 4 below. It shows that FMC needed 449 simulations to identify the worst samples in a 3σ run and 570 simulations to find the 4.5σ point in a 1M MC run out of 2,000-point MC runs.

Figure 4: Spectre FMC Analysis to identify the 3σ value out of a 2,000-point MC runs for PLL

The plots on the right are from an FMC run to identify the 3σ value. The graph on the right-hand side shows the zoomed-in tails.

Summary

Increased process variations and mismatches in advanced technologies need faster and more accurate statistical simulations to ensure target yield for complex systems. Cadence's Spectre FMC Analysis uses ML and advanced statistics to estimate failures and yield accurately. It enables designers to explore and debug worst-case design failures early to avoid expensive design rework. The high-sigma monte carlo analysis capability provided by Spectre FMC is accurate, reliable, and scalable for analog/mixed-signal, RF, and I/O blocks, memories, and bit/standard cells.

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