Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation problems that need fixing. Should you call the travel agent to see if you can still buy travel insurance?

The fact is, for design engineers, ECOs are a fact of life. Many digital design environments have implemented fast and efficient ECO flows, which can accommodate pre and post mask ECOs.  In the older generation of mixed signal designs, the analog portion of the design was partitioned off, creating physical boundaries between the digital and analog content. This made it easier to incorporate changes in the digital or analog content without worrying too much about creating problems in the interfaces between the two.

Challenges of ECO Management

Today's mixed signal designs are implemented using a hierarchical methodology, and it is not uncommon to find analog blocks residing inside digital functions that control analog signals. What used to be a purely digital block is now incorporating such things as power management features, which introduce analog content in these blocks.

Two of the questions most often asked in the context of mixed signal designs are:

• How to reduce the likelihood of design re-spins due to mixed-signal implementation errors or miscommunication between the analog and digital teams.
• How to perform ECOs due to necessary design changes using a mixed-signal database.

The implementation of a mixed-signal design may incorporate both netlist and schematic driven methodologies. This is where parts of the design are represented by a netlist while others are represented as schematics. For large mixed signal SoCs, it is very important that the results from analysis of the top level floorplan be used to drive implementation of the many blocks in the design, regardless of whether a particular block is represented by a schematic or a netlist.

In addition, a methodology is needed to allow for better communication between the top level designer and those in charge of implementing the many blocks in the design. Without this methodology, there is always a chance that the design of blocks end up invalidating the analysis done at the top level.

How OpenAccess Supports ECOs

The Cadence mixed-signal solution offers a concurrent mixed-signal floorplanning solution, which allows for efficient, frequent and clear exchange of data between the top level designer and those designing the lower level blocks. The solution is implemented on the OpenAccess (OA) database, and allows for the exchange of floorplanning, placement and routing constraints. In addition, the environment offers the capability to imbed mixed-signal IP blocks with constraints that are used when instantiating such IPs within a design, regardless of the environment used for implementing the top level of the design.

To address the challenges of performing ECOs on mixed signal designs, Cadence has implemented powerful ECO functionalities that perform ECOs on the actual OA database, containing both custom and P&R objects. For example a design containing P-cells can be ECO'ed in the Encounter environment without the need to separate out the custom objects in the design. The following figure depicts the pre-mask ECO flow that implements changes made to the netlist.

The first step in this flow is to open the pre-ECO database in the Encounter Digital Implementation System (EDI) using the restoreOaDesign  command. As you can see, there is no need for a LEF technology library, as a common OA PDK can be used for the EDI and Virtuoso environments, containing all technology information needed for the mixed-signal implementation flow.

A Verilog netlist is then extracted from the OA database, which can contain P-cells, if they existed in the design. The Verilog netlist can now be edited to make the necessary changes. In EDI, the command ecoOaDesign can now be used to read in the changes in the Verilog netlist, while maintaining the floorplanning, placement, routing, and other aspects of the pre-ECO OA database.

If new instances have been added to the design, and the design takes advantage of low power features, additional steps are required to repair the power domain, using CPF. At this point the design is ready to go through ECO placement, or the user can optionally use other features of EDI to guide placement of the new unplaced cells in the design. Once ECO routing is completed, and any DRC issues resolved, the user can save the full OpenAccess database, with ECOs.

Similar flows exist for post-mask ECOs, as well as ECOs to the OA database, using the Virtuoso environment.

Benham Farhat