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custom/analog
Virtuoso
Custom IC Design

Virtuoso Studio: Faster Than the Fastest - Custom Platform For the Next Decade

6 Jul 2023 • 4 minute read

Virtuoso Studio

Our new AI-powered custom design solution, Virtuoso Studio, leverages our 30 years of industry knowledge and leadership providing innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries. In this blog series, learn how the best analog design tools just got better to help you keep pace with your challenging design issues. 

By Olivier Arnaud, Product Engineering Group Director, Cadence Design Systems

We are witnessing many exciting innovations leading to the creation of new applications and resulting in rising customer expectations. Such technological advancements have resulted in more functionality and increased complexity over SoCs and demand high performance. To keep up with the design challenges and enhance performance, the analog design world is evolving, and so is Virtuoso technology. Virtuoso - the fastest tool for custom IC design and layout, just got Faster with a new revision, Virtuoso Studio. It helps solve custom layout creation problems with improved infrastructure, innovative, productive features, and seamless integration of Cadence tools into Virtuoso Studio. This blog introduces performance improvements and a diagnostic center in Virtuoso Studio to achieve results faster and overcome performance bottlenecks.

Challenges

With the increasing complexity of SoCs, designers face many challenges while using the traditional schemes, such as

  • Reduced productivity
  • Performance issues while loading and displaying hierarchical design
    • Finding the root cause of performance issues on the fly
    • Finding performance and environment debugging utilities
  • Issues with the extraction during abstract generation
  • Power/Ground Nets are usually very large in designs
  • The legacy extraction engine is very slow
  • Shape-based short detection adds to slow extraction runtimes
  • The algorithm causes stack overflow problems on machines with limited RAM

Solution

Cadence introduces Virtuoso Studio to overcome all the challenges mentioned above. It offers performance measurement/enhancement and diagnostics to speed up the complete process (improve TAT and productivity). Virtuoso Studio resolves such issues and comes with the below-mentioned improvements over the earlier generations.

  • Core editing command improvement: Core editing commands are improved by revamping the code or multithreading. For instance, the layout connectivity extractor can now run on many threads.
  • Benchmarks: To measure performance gain, Virtuoso Studio offers a set of benchmarks based on generic data (generic PDK/design and generic script) to customers in the Chip design, Analog design, and Chip assembly segments/flows. Customers can ascertain the performance using these benchmarks or may contact Cadence in case of any deviation.
  • Diagnostic Center: This is a comprehensive environment in Virtuoso Studio that performs
    • Health monitor – Continuously monitoring Virtuoso in real time to inform the user about the issues and the originating causes(internal or external)
    • Provides a debugging environment to report the overall status of the environment.

Key Technologies and Benefits of Virtuoso Studio

Virtuoso Studio, with diagnostics and performance enhancement, offers designers many benefits. A few of the key technologies and features are mentioned below:

  • Debugging utilities are integrated into the diagnostic center. It improves usability as all the performance and environment debugging utilities can be accessed from a single UI, i.e., diagnostic center.
  • The health monitor continuously tracks Virtuoso and system pulses and provides the status of essential vitals such as system resource charts and CPU/Memory consumption. In addition to recording callstacks and terminating Virtuoso, the dynamic status of the tool is shown to the user in the health monitor.

Users can quickly debug and fix the issues using this proactive support.

  • The hierarchical cache in Virtuoso Studio helps improve the performance and resolves the performance issues while loading and displaying hierarchical design.
  • Improved extraction performance and up to ~5X performance increase for power net extraction.
  • Multithreading (MT) addition to Xstreamout offers 2X speed up (with four threads)

Performance Enhancements Using Virtuoso Studio

To highlight how various features embedded into Virtuoso Studio help improve performance, we have used customer and internal data in the chip finishing, analog/custom IC, and chip assembly flows. Below are the various design details and their respective gains that show improved performance over the earlier version of Virtuoso ICDAVM20.1ISR. The results show significant performance gains of up to 3X while using the customer data in chip finishing flow, and up to 1.8X and 2X are noticed in the analog/custom IC design flow and chip assembly flow. The differentiated automation features in Virtuoso Studio provide greater productivity benefits over and above the performance gains noted below.

Node

Data

Gain (x)

Design Type

Design Details

Mature

CustomerData2

2.1

Chip Finishing

Top- Inst:5.4M, Nets:5.7M, Pins:391, Total-Inst:5.4M, Rect:32.9K, StdVias:2.86M, CustomVias:8.69M, PathSegs:106.6K, Cell:552

Mature

CustomerData3

2.9

Chip Finishing

Top- Inst:254.5K, Nets:554, Total-Inst:2.9M, ArrayInst:4513, CustomVias:1.39M, Cells:4.36K, PathSegs:424K

Mature

CustomerData5

3

Chip Finishing

Top- Inst:1.3M, Nets:1.3M, Pins:23.6K, Total-Inst:1.39M, polygons:192, Rect:104k, StdVias:696k, CustomVias:22.3M, PathSegs:27.3M, cells:1.5k

Advanced

CustomerData7

1.6

Analog/Custom IC

Top-Inst:1.9K, Nets:68, Pins:1.4K. Total-Inst:2.7K, ArrayInst:28, Polygons:64,Paths:386, Rect:148.7K, StdVias:25.3K, PathSegs:2.9K, Cells:585

Advanced

InternalData1

1.4

Analog/Custom IC

Top-Inst:20.3K, Nets:1.6K, Pins:8 Total-Inst:20.3K, Rect:255.3K, StdVias:45.5K, Cells:45

Advanced

InternalData2

1.8

Analog/Custom IC

Top-Inst:6K, Nets:621 Total-Inst:6K, Rect:8.2K, Cells:8

Mature

InternalData3

2

Chip Assembly

Top- Inst:5.6K, Nets:9K, Pins:2.9K, Total-Inst:14.2K, Array Inst:100, Polygons:1.3K, Paths:15.4K, Rect:335.6K, StdVias:93K, CustomVias:15.4K, PathSegs:175.7K, Cells:1376

Mature

InternalData4

1.8

Chip Assembly

Top: Inst:200/22.6K, Nets:11.6K, Pins:11.6K, Total-Inst:22.2K, Array Inst:400, Polygons:404, Paths:7.4K, Rect:44.1K, StdVias:427.3K, PathSegs:696K, cells:342

Mature

InternalData5

1.9

Chip Assembly

Top- Inst:6, Nets:201, Pins:71 Total-Inst:45.8K, polygons:37, Paths:36.4K, Rect:839.7K, StdVias:52K, CustomVias:151.6K, PathSegs:124.7K, Cells:2.5K

Summary

With the increasing complexity of SoCs, designers face many challenges while using traditional schemes; by leveraging Virtuoso Studio, designers can overcome the challenges and improve productivity. It offers performance measurement/enhancement and diagnostics to speed up the process and improve TAT. The core edit commands, health monitoring, and diagnostic center improvements enhance the performance gain at the advanced and mature nodes and help improve productivity, TAT, and usability.

In other words, with the new offerings and features, the Virtuoso Studio is 'Faster than the Fastest.'

Learn more about Virtuoso Studio.


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