Virtuoso Meets Maxwell: Full 3D Analysis of Traces and Bond Wires in an RF Module

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Welcome to another post about how easy it is to run full 3D analysis in the Virtuoso RF Solution!

In previous posts I have focused on flip-chip ICs. So today, we are going to focus on a bond wire attached IC, another common scenario in RF modules. We will see that simulating an RF module with a wirebonded IC using Clarity 3D Solver is just as easy it is for a flip-chip attached die. All we have to do is pick the traces we want to simulate - and the tool takes care of the rest, including the port setup!

Here is the RF module we want to simulate.

In Virtuoso Layout Suite EXL, I switch my workspace to “Electromagnetic”. This pulls up the Electromagnetic Solver Assistant on the right side of the layout canvas. We can use this assistant to create as many models as we want and then launch Clarity 3D Solver to run simulations. Each model contains the traces I want to simulate, as well the ports and optional cutting boundary. In this example, I want to model the RF input path from the LGA pad up through the bond wire into the IC. (Note, to keep the 2D view clean, only the top package layer is shown)

The RF input net contains an SMD. As a result, ports are automatically inserted on the SMD pads.

Finally, ports with PEC plane will be automatically inserted at the RF input connection on the IC and the LGA package. This is summarized on the “Coax” tab.

We can set up two types of ports on the IC end of a bond wire:

• Coaxial Ports
• Vertical Ports

Connecting a Bond Wire using a Coaxial Port

By default, in Virtuoso RF Solution, a PEC plane with coaxial ports is generated. This can be seen below. In blue is the RF input net from the LGA pad, ending in a vertical port at the SMD pad. In orange is the other portion of the RF input, from another vertical port to the bond wire. At the die pad, a coaxial port was inserted to the PEC reference plane. The reference plane is grounded by the wires on the GND net.

Given below is a closer view of the signal wire with a coaxial port and the two ground wires directly connected to the PEC plane.

Connecting a Bond Wire using a Vertical Port

With the flip of a switch in Layout EXL, we can generate vertical ports instead of coaxial ports for the bond wires. In this case, the PEC plane is inserted below the die pads and vertical ports are inserted. For ground wires, vertical PEC sheets are used to provide the return path from the IC to the module.

Here is another closer view, this time of the vertical ports from the pads down to the PEC plane. The two green wires are the current return and have a port with short termination.

This concludes the setup of a wirebonded IC in Virtuoso RF Solution.

Now, would you not call that an effortless port setup? All we had to do was pick the traces of interest, and decide between coaxial ports or vertical ports for the bond wires. Everything else was automatically done for us.

Johannes Grad

Related Resources

• Virtuoso RF Solution
• Virtuoso MultiTech Framework Guide
• Virtuoso RF Solution Guide
• Virtuoso Electromagnetic Solver User Guide
• What’s New in Virtuoso

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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