'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Hi everyone, I hope you have been enjoying our Virtuoso Meets Maxwell series. Within a very short amount of time we have had a number of prolific blog authors contribute to our series, with the latest contribution from one of our senior Application Engineers, Kristin Fullerton, pitching in with the blog titled Add Some MAGic to Your ElectroMAGnetic Analysis. In this blog, Kris has walked us through the integrated flow inside Virtuoso RF to run Electromagnetic (EM) analysis with AXIEM.

I am going to take Kris’ blog as a great starting point and write a multi-part blog with some of the additional details of the flow.

By the way, I should have introduced myself. My name is (Sutirtha) Kabir and I have been working as a Product Engineer at Cadence for almost 16 years. My current responsibility allows me to work as a Product Engineering Architect for Virtuoso RF and work with our Field Application Engineers and Customers alike to define and improve the flow.

If you have been following our series, you may have realized that we have emphasized design automation as a linchpin for the entire Virtuoso RF solution. We challenged our software development team to revolutionize acceptable/traditional design flows that are widely used but are manual, inefficient, time consuming, and error prone. And boy, have they stepped up magnificently!

One of the areas where we have broken the norm is the integrated flow for running EM analysis. I know I am repeating myself, but if you haven’t read Kris’ blog, I highly encourage you to read it, because she really paints a very good high-level picture of the flow.

OK, so you are convinced now that you want to try out our flow. How do you start? What are some of the details? Are there any tips for best practices? That’s what I will try to tell you in this miniseries.

If you have been using EM analysis engines for a while, then you know that the whole flow involves a number of steps. These steps include:

1. Process setup
2. Geometry selection
3. Port setup
4. Simulation setup
5. Using results

In today’s blog, I will discuss the process setup and will confine the discussion to IC layouts (as opposed to package or board layouts - more on those some other time).

Process Setup

Typically, in this context, process means the following information:

1. Bulk Si thickness, dielectric constant, and conductivity.
2. Inner layer dielectric (ILD) thickness, dielectric constant, and conductivity.
3. Metal layer vertical location, thickness, and conductivity.
4. Via layer names, start and stop metal layer names.
5. Boundary conditions – open or closed at the top and the bottom.

What can be a source for this information?

• Design Rule Document (DRM) or Electrical Specs
• A qrcTechFile or ict file – these files are typically part of your process design kit (PDK)
• You can also create this file from scratch, although that can be laborious step.

Does the OA tech file have this information? No.

Defining Bulk Silicon: Typically, the bulk Silicon information is not included in the process files that are part of the PDK. The user will have to enter the thickness, permittivity, and conductivity (in Siemens/meter). A few helpful notes about calculating conductivity:

• If the sheet resistance (Ohm/square) of the metal layer is reported, then, in order to convert that to conductivity (Siemens/m), one can use the following equation:

  Conductivity = 1 / (thickness X Sheet Resistance)

• The thickness is usually reported in um and has to be converted to meter for the above equation.
  
  
• If the resistivity or rho (m/Siemens) of the metal layer is reported, then, in order to convert that to conductivity (Siemens/m), one can use the following equation:

 Conductivity = 1 / Resistivity
 Note: Resistivity = thickness X Sheet Resistance

Typical IC Stackup: Even though the process can be automatically set up by loading an ict file or qrcTechFile, however, it’s good to understand the setup.

The Z locations on the right-hand side are the elevation of the dielectric layers as well as the metal layers. Reference (Z = 0) is at the bottom of the IC. Only one ILD is shown in this figure. Typical IC processes can have more than one (as high as 20) ILDs.

The dielectric layers need to have thickness, permittivity (dielectric constant), and conductivity. In almost all Si-Ge and CMOS processes, only the Si layer has finite conductivity and the other dielectric layers have zero conductivity. Finite dielectric blocks inside the bulk Si (p-wells, n-wells, etc.) are not modeled.

The metal layers need to have elevation (with reference to Z = 0), thickness, and conductivity. The elevation automatically determines the relative location of the different metal layers in the dielectric stack.

Modeling a Metal Layer as Thick versus Thin Metal: Metal layers are ALWAYS defined with thickness (t) and elevation (h1) in the process stackup. When the metal is treated as thin, an infinitely thin metal is assumed at h1. When the thick metal option is turned ON for a particular metal layer, that metal is treated as thick. This treatment can be viewed as expanding the metal “up” (as opposed to expanding “down”). The same stackup can be used for thick/thin modeling.

Hopefully, you are getting a better understanding of some of the nuances of setting up the process. In the next part, I will pick it up from here and discuss the other parts of the flow. Until then, as Tigger would say, TTFN.

Related Resources

• Virtuoso RF Solution
• What’s New in Virtuoso (ICADVM18.1 Only)

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuoso Meets Maxwell posts.


Sutirtha Kabir