Virtuoso Meets Maxwell: How to Perform an XOR Operation on a Package Design Interchanged Between SiP and Virtuoso RF Solution?

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

While Allegro Package Designer Plus with its SiP Layout Option is, and continues to be, one of the most complete solutions for package design, Virtuoso RF Solution allows module layout authoring capabilities inside the Virtuoso System Design Platform. The Virtuoso RF Solution offers a powerful suite of IC and package co-design capabilities, such as Edit-In-Concert, cross-fabric net probing, and bump optimization. Virtuoso RF Solution co-design environment reduces the design cycle and eliminates error-prone manual steps to align an IC with a package. If you are co-designing the package and IC, you might want to use both the Allegro and Virtuoso platforms to complete their design.

Today, I want to talk about the very common task of the design XOR operation in the context of interoperability.

There is often a need to ensure design data remains the same, that is, independent of the type of design (IC or package). The same motivation holds for package design data. While you benefit from the Edit-in-Concert capabilities in Virtuoso RF Solution, taping out manufacturing data from Allegro Package Designer Plus requires an XOR functionality to compare package design data, but there is a major obstacle. The design data is stored in the .sip format in Allegro Package Designer Plus and stored in OpenAccess data format in the Virtuoso environment. In fact, there can be two design database formats for a design.

While interoperability ensures translation from one format to the other without any loss, you might want to check at any time if design data represented in the .sip format and the OpenAccess format do match. Therefore, we have introduced a very effective layout XOR capability in Virtuoso ICADVM 20.1 ISR19 to compare the OpenAccess layout view in Virtuoso RF Solution against the .sip/mcm/brd file in the Allegro platform. The XOR capability takes into account the differences in layer names and purposes, voiding model, and Database Unit Per User Unit differences, and provides a convenient difference visualization capability in the Virtuoso environment through markers that are managed in the Annotation Browser. Not only a GUI has been provided to run the XOR functionality, but also a SKILL API is available for use. 

Let’s delve deeper into the XOR functionality. 

We want to know if there are differences between the design shown here.

It is a well-structured and an intuitive GUI. Specify the .sip design file and select the OpenAccess design view to compare with.

It is recommended to store the XOR operation results in a new library referenced to package library of the module layout design input. The XOR functionality needs to add some additional marker layers to technology file definition. Otherwise, you might get confused by such additional layers in the palette when doing package design edits.

You can set a few options while it is recommended is to go with the default. For purpose of this blog, the XOR operation is done for all layers and with reduced tolerance.

The XOR operation completes very fast and the XOR result view opens.

The Layers assistant is enabled automatically and all layers that are set by default as Valid are shown. A few layers are added to view the XOR results. Only the layers defined by the OpenAccess input are subject for the XOR operation. The SiP-defined layers are not relevant. Therefore, for the XOR results, review only the Used Layers because these shapes represent the differences found.

Such additional layers indicate differences that have been found. In the above-mentioned example, the differences are found not only on the M4 and M2 conducting layers but also on the assemblyBoundary layer.

See the picture below to understand the meaning of these layers by looking only at the XOR results for the M4 layer.

Shapes drawn with*_SIP extended layers represent the outline of shapes in a SiP layout. *_OA represents the outline of shapes for same layer in a Virtuoso RF Solution design. Any *_SiP related shape is tagged by adding prefix Sip_ to its original connectivity, while the Virtuoso RF Solution shapes do not have any connectivity. That helps to identify the shapes that belong to the SiP layout or Virtuoso RF Solution inputs.

The layer M4 with purpose drawing represents the XOR differences if shapes from the SiP layout and Virtuoso RF Solution do not overlap.

The MISC tab on the Annotation Browser assistant also lists all reported differences and provides detailed review by easy selection, zooming in, and highlighting capabilities.

To conclude, a right-shifted M4 dynamic shape in Virtuoso RF Solution causes this difference.

Let’s look at a few more differences on the M2 layer results.

Many voiding shapes differences are reported. Having these is almost inevitable because Virtuoso RF Solution and SiP Layout Option use two different voiding algorithms that cannot be aligned.

Good to see below, when zooming to one void difference it shows the mentioned Sip_GND connectivity, meaning SiP design shape is bigger than the Virtuoso RF Solution design shape.

Next example shows a typical routing difference in M2.

As the XOR operation was not only limited to conducting layers but also included all layers related to the Virtuoso RF Solution placement layer, assemblyBoundary for SMD components has been flagged.

These are dummy differences as such component and placement layers are usually not mapped 1:1 to the SiP layout layers. Instead, it is done by a complex mapping including several layers. For illustration, view the DFA_Bound_Top layer for same shapes in SiP Layout Option. As the Allegro Import and Export functionality take care of correct mapping of these placement and description layers, it is recommended to run the XOR operation only for conducting layers (default set in UI).

If you need or want to know more about layer correspondence during interoperability, ask your Cadence representative for details.

Let me close my blog with how it looks if both design representations match. There is no smiley or layout versus layout matched message, simply no shapes are present in XOR layout view. You can verify the Used Layers in the Layer Palette.  If no layers are used, it means designs do match!  

Thanks for your interest! I hope, you enjoyed the blog and do remember this handy utility to run XOR, whenever you want to ensure shape matching between SiP and OpenAccess design representations.

Related Resources

Datasheet	Virtuoso RF Solution What’s New in Virtuoso
Product Manual	Virtuoso MultiTech Framework Guide Virtuoso RF Solution Guide Virtuoso Electromagnetic Solver Assistant User Guide
Videos	Comparing a SiP File with an OpenAccess Layout
Free Trials	Virtuoso RF Solution - Module Layout with Edit-in-Concert Virtuoso RF Solution - EM Analysis Virtuoso RF Solution - Physical Implementation Flows

For more information on Cadence circuit design products and services, visit www.cadence.com.

Kai Schiller

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About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching! To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.