IEEE Recognition of Cadence Software at DAC 2016

Cadence was awarded with the IEEE Donald O. Pederson Best Paper Award—EDA’s most prestigious recognition of its kind—for the best paper published in IEEE Transactions on CAD over the past two years. 

The paper, “Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space”, was part of a collaboration with Carnegie Mellon University. The award itself recognizes the best paper that has been published over the past two years based upon general quality, originality and subject matter.  The paper describes a new algorithm to calculate the rare failure rate with consideration of variability and uncertainties in manufacturing process, allowing companies to validate their integrated circuits with significantly less simulation time.

The algorithm is part of the Virtuoso Variation Option and is available today.  The feature, named Scaled-Sigma Sampling, is very simple to use.  You can learn more about the technology by reading the blog overview, by consulting Cadence documentation or have a chat with your field support representative to schedule a demonstration.