Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal Modeling?

In this Knowledge Booster blog, we talk about Real Number Modeling with Verilog-AMS (also called wreal Modeling) and explore how to model analog or mixed-signal blocks using wreal language. We also introduce you to the two-day course on Real Number Modeling with Verilog-AMS and to the videos and training materials that can help you understand different wreal modeling techniques.

Wreal (wired-real) is a subset of Verilog-AMS language useful for modeling continuous analog or mixed-signal designs using its discrete sampled real values. Wreal modeling is a mixed approach, borrowing concepts from analog and digital simulation domains. The values of signals are continuous, floating-point (real) numbers, as in the analog world. However, time is discrete, like in the digital domain, implying that the real signals change values based on discrete events at specific time points. Verilog-AMS language and System Verilog language share Verilog as their common subset as shown in Figure 1 below. Inside Verilog-AMS there is a specific feature called wreal – a wired real port, that allows it to connect between the digital core and analog core. They are discrete real variables. We can use the wreal data type to drive real values (like 2.20, 1.1e30 etc) on ports. Wreal or wired-real is a wire that is of type real, connecting between blocks. Unlike a wire, a wreal can be driven by multiple drivers at a time. It is used to model wires that carry analog currents and voltages.

Figure 1:  Wreal: A subset of Verilog-AMS Language

Digital Mixed Signal (DMS) Technology to Speed Up Mixed-Signal Simulations

Analog simulation gets slower and slower as the number of transistors and devices increases in a design. On the analog side, the simulation time required increases exponentially as the complexity of the circuit increases and simulation time goes up to infinity when you try to get the analog systems too big. On the digital side, the simulation really does not slow down like an analog simulation when the number of components increases. Simulation time on the digital side is a linear function of circuit complexity.

Now, if you can actually take some of the analog blocks and move them over the digital side, and evaluate the values of electrical (voltage/current) signals at discrete time steps, you can get a much more efficient simulation for the analog blocks. It is hundreds or thousands of times faster in simulation, but as things get bigger, they grow only linearly and do not enter to a super linear pace and thus avoid the simulation time going up to infinity.

Thus, digital representation of Mixed-signal design comes as a solution to the problems associated with analog and mixed signal simulations when running on big systems, where you may need only high-level transfer characteristics of those blocks to verify the top-level functionalities. For this purpose, you can model analog circuits using Real Number Modeling (RNM) languages like Verilog-AMS wreal (VAMS wreal) or SystemVerilog Real Number Modeling (SV-RNM).

This allows simulation using only the digital solver (Xcelium Logic Simulator) along with the Xcelium Digital Mixed-Signal (DMS) App to avoid the slower analog simulation and enabling intensive verification of mixed-signal design within a short period. To know more, check out the videos on What is Xcelium Mixed-Signal App ?

This method of modeling analog signals using its sampled data points to do event-driven digital simulations is called Digital Mixed Signal (DMS) Technology.

Traditional analog simulations using analog solvers like Spectre^® would take several days to complete a mixed-signal simulation using SPICE-level accuracy for even a comparatively low number of digital clock cycles, such as an analysis of the performance of a 14-bit ADC+ 14-bit DAC over its full range of sample values to see how the control logic behaves. If you model the same thing with RNM (VAMS wreal or SV-RNM) you would get the result in a couple of seconds! Meaning, even fairly sophisticated analog models when modeled with RNM can run within a few seconds and still have it doing all the required operations.

General Procedure to Create Wreal Models

If you want to create a wreal model for an analog or mixed-signal block, here's the general procedure:

Step 1: Identify all the functionalities of the analog blocks that are to be modeled. We generally choose the highest hierarchical level of that block and model only the analog functionalities using its unidirectional transfer characteristics.
You can watch the  training video Who Creates the Analog Models? to decide who in the team can create wreal models and what functionalities are to be modeled, given an analog or mixed-signal block. 

Step 2: After identifying all the functionalities to model, you need to define the inputs, outputs and any other required headers like parameters and create any variables that would be required to use inside the block. After that, initialize the variables if it needs initializing.

Step 3: Find out the equations for the input versus output relationship and write the code accordingly. Note that, unlike in behavioral models (written in Verilog-A or Verilog-AMS Electrical), in wreal modeling you would require to write separate equations for voltage and current signal of  a block and drive it on wreal pins, as there is no concept of electrical nodes in digital realm.

In wreal models, you are building a sampled data-style representation of the continuous signal, and so the output of the block is updated only at specific time intervals. You must figure out when you're  going to drive the output port. Since this is a discrete system, you must pick a time increment to define how often you want the output to be recomputed and driven on the ports. A common way is to drive the result of the output equation on the port every certain number of nanoseconds.

As mentioned, wreal model requires a discrete simulation environment for simulation and no analog solvers are utilized. Thus, the wreal language looks a lot like digital Verilog (Verilog-D) with the one simple addition that instead of the data being bits, the data can also be real numbers. Thus, wreal takes Verilog-D and extend it to allow real numbers to pass between ports. You will be using initial and always blocks to describe the behavior of these real ports as opposed to in a Verilog-A type approach, where you'd be using an analog block to describe voltage-current interaction, and it is given to Spectre, an analog solver. In contrast, for wreal models, only digital solvers are required to run simulations. For users using Verilog-AMS wreal, Cadence has built-in wreal nettypes, such as wrealsum, wrealavg, wrealmin, and wrealmax, that enable Verilog-AMS code reuse and ease the migration of wreal model to SystemVerilog Real Number Model. To know more about how to create SV portable wreal models, watch the video on Built-In wreal Nettypes (Useful for SV Portability)

When building the model using behavioral codes with Verilog-AMS wreal, note the following points:

• Wreal pins can't be driven directly with behavioral code because they are not variables, they are nets. Only assign statements can drive them.
• Use always procedural blocks and continuous assignments (assign statement) to describe the behavior of the analog signals. And take care not to use any analog procedural blocks, discipline definition or usage, or any electrical nets to implement functionality in wreal.
• You cannot use analog operators and equations inside a wreal model. For example, you shuold not use transition filter, slew filter, time derivative operator (ddt), and time integral operator(idt). Instead implement those analog operations using digital operators and built-in mathematical functions such as ln(x), exp(x), sqrt(x), sin(x), cos(x), sinh(x), pow(x,y), min(x,y) etc.
• You may require analog expertise to understand how to accurately convert analog operations to discrete format.
• Remember that wreal modeling is applicable only if analog blocks are modeled at a high enough level that unidirectional transfer characteristics make sense. 

You can also go through the example of a stimulus generator written in VAMS-wreal code for better understanding.

Now, I highly recommend you to go ahead and take the free online course on Real Modeling with Verilog-AMS (Version: 22.03, Course Duration: 2-days, Intended Audience: Analog/Mixed-Signal IC Designers, Analog/Mixed-Signal IC Verification Engineers, Digital Modeling and Verification Engineers) to learn how Real Number Modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification.

In this course, you can learn how to model analog block operation as discrete real data for high-performance digital-centric, mixed-signal SoC verification. You can explore the advanced capabilities of wreal by examining how wreal connections are resolved in mixed designs. You can create Verilog-AMS wreal models and verify their functionality and performance, using the Spectre^® AMS Designer or Xcelium^® Simulator with Mixed-Signal Option in both the command-line and the Virtuoso^® Analog Design Environment.

What’s Next?

On the  Cadence Learning and Support site (login required) you can:

• View the Real Modeling with Verilog-AMS Training Byte Channel
• Take the free online course Real Modeling with Verilog-AMS
• Get Your Skills Noticed with a Digital Badge from Cadence Training by passing the exam course Real Modeling with Verilog-AMS
• Visit the One-Stop Knowledge Resource for Mixed-Signal Verification to get more resources on mixed-signal verification and modelling.

Related Resources

Training Bytes (videos)	How Do You Create a wreal Model of a Sinusoidal Source? How to Model an Analog Filter in wreal? Modeling a Second Order Low Pass Filter in wreal. Modeling a Voltage Controlled Oscillator Wreal Modeling of a Programmable Gain Amplifier Modeling A2D and D2A Converters in wreal
Online Courses​	Behavioral Modeling with Verilog-AMS Command-Line-Based Mixed-Signal Simulations with the Xcelium Use Model Real modeling with SystemVerilog Analog Modeling with Verilog-A

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Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material, on a regular basis.

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Mohammed Jaseem

On behalf of the Cadence Training team